2/24/2008 9T6WP
BCM7405
Preliminary Hardware Data Module
Functional Description
06/29/07
Bro a d c o m C o rp o r a ti o n
Page 1-64
MIPS4380 Processor Core
Document
7405-1HDM00-R
M
ICRO
-A
RCHITECTURE
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Standard MIPS32 six-stage pipeline
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Multiply-divide unit (MDU)
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Latency of three and four cycles, respectively, for 32x32-multiply and multiply-accumulative operations
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Max issue rate of one 32x32 multiply and multiply accumulate operations every clock
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Divide instructions: 3 to 18 cycles of latency depending on the dividend size
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Each of the TPs has separate set of Hi/Lo registers but they share the MDU execution unit
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Dynamic branch prediction with a 4K-entry branch history table and a 4-entry call-return stack
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Set associative instruction and data caches
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Split I-caches: 2-way set associative, 32 KB for each TP.
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D-cache: 4-way set associative, 64 KB; segment- and page-based write-thru or write-back store policy. The D-cache
is shared by both TPs.
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Both caches: 64-byte line size, LRU (least recently used) replacement algorithm
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A cache store buffer that allows the data cache to be continuously accessed and stored.
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L2 cache holding lines displaced from the instruction and data caches
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8-way set associative with a capacity of 128 KB, a line size of 64 bytes, and LRU replacement algorithm
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Copyback Gathering: can combine one to four consecutive modified lines to a block to send to the memory
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Readahead cache (RAC) to prefetch and stage the cache lines ahead of cache misses
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4-way set associative with a capacity of 8 KB, a line size of 256 bytes, and LRU replacement algorithm
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Each TP can independently set up prefetching controls
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Separate write buffers for non-cacheable stores and copybacks
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Stage up to 16 non-cacheable stores, each store can be up to one word
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Stage up to 16 copyback L1 lines
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Low-Latency Memory Bus (LMB) as a high-performance system option
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Direct memory connect
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All the cache misses go through LMB, the rest go through the prevailing system bus
EJTAG D
EBUG
S
UPPORT
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MIPS-standard software debugging with software breakpoints
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Non-intrusive hardware single stepping
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Non-intrusive hardware breakpoints on virtual addresses, physical addresses, and data values: two instruction
breakpoints, two data breakpoints, and two data value breakpoints.
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The EJTAG debugging facility is performed on one TP at a time
