2/24/2008 9T6WP
Preliminary Hardware Data Module
BCM7405
06/29/07
Bro a d c o m Co rp o r a ti o n
Document
7405-1HDM00-R
Page xi
L
IST
OF
F
IGURES
Figure 1-1: Functional Block Diagram ............................................................................................................. 1-7
Figure 1-2: Video Data Flow Diagram ............................................................................................................. 1-8
Figure 1-3: Data Transport and Broadcom Security Processor Block Diagram ............................................ 1-14
Figure 1-4: Data Transport I/O Connections Diagram ................................................................................... 1-16
Figure 1-5: Advanced Video Decoding Module Block Diagram..................................................................... 1-32
Figure 1-6: Audio Block Diagram................................................................................................................... 1-33
Figure 1-7: Video and Graphics Block Diagram ............................................................................................ 1-38
Figure 1-8: Video Display Engine Block Diagram.......................................................................................... 1-39
Figure 1-9: DNR Position in BVN .................................................................................................................. 1-43
Figure 1-10: Memory-to-Memory Compositor Block Diagram ....................................................................... 1-45
Figure 1-11: Stripe Example .......................................................................................................................... 1-46
Figure 1-12: Color Keying Flow ..................................................................................................................... 1-48
Figure 1-13: VEC Block Diagram .................................................................................................................. 1-52
Figure 1-14: RF Modulator Block Diagram .................................................................................................... 1-56
Figure 1-15: Memory Controller Partition ...................................................................................................... 1-60
Figure 1-16: Block Diagram of the CPU ........................................................................................................ 1-65
Figure 1-17: Little and Big Endian Byte Ordering .......................................................................................... 1-69
Figure 1-18: Flash IR Scheme Example........................................................................................................ 1-72
Figure 1-19: IR Blaster Block Diagram .......................................................................................................... 1-72
Figure 1-20: Analog Front End of UHF Receiver with External Components................................................ 1-74
Figure 1-21: Digital Front End of UHF Receiver ............................................................................................ 1-75
Figure 1-22: UART Functional Block Diagram .............................................................................................. 1-76
Figure 1-23: Asynchronous Serial Data Waveform (01001011 Data, 8-bit Character, Even Parity) ............. 1-76
Figure 1-24: Variable-Frequency PWM Generation Diagram........................................................................ 1-80
Figure 1-25: Smart Card Interface Block Diagram ........................................................................................ 1-81
Figure 1-26: M-Card CPU Interface............................................................................................................... 1-82
Figure 1-27: MCIF Interfaces......................................................................................................................... 1-83
Figure 1-28: EBI Synchronous Read Cycle Between Two PCI Cycles ......................................................... 1-85
Figure 1-29: EBI Asynchronous Read Cycle Between Two PCI Cycles ....................................................... 1-86
Figure 1-30: EBI Asynchronous Write Cycle Between Two PCI Cycles........................................................ 1-87
Figure 1-31: EBI Synchronous Write Cycle Between Two PCI Cycles ......................................................... 1-88
Figure 1-32: SATA Core Block Diagram........................................................................................................ 1-90
