2/24/2008 9T6WP
BCM7405
Preliminary Hardware Data Module
Functional Description
06/29/07
Bro a d c o m C o rp o r a ti o n
Page 1-62
Memory Controller
Document
7405-1HDM00-R
DRAM T
RANSACTION
L
AYER
C
ONTROLLER
Arbitration
The arbitration method is an extension to the well-established method of Rate Monotonic Scheduling. Arbitration uses a
combination of priorities, round robin, and block out counters. Clients with real-time scheduling deadlines are served via fixed
priorities. Block-out counters serve to ensure that real-time clients are well behaved and do not interfere with the ability of
other clients to meet their deadlines. Round robin arbitration serves all clients and functions that do not have real-time
deadlines, including extra requests by real-time clients that are temporarily blocked by block-out counters. Round robin
arbitration operates at the lowest priority, and it serves to allocate all available DRAM clock cycles while the DRAM is not
being used by fixed-priority clients.
Buses
The BCM7405 memory controller is connected to the various modules within the device using system buses. The main bus
has a 256 bit-wide data-path.
DDR-SDRAM Memory Image Organization
The advanced video decoder (AVC/MPEG/VC-1) cooperates with the DRAM controller optimizes the performance of the
DRAM controller when decoding the more complex advanced formats.
Digital Video Compression Standards
Video compression standards such as AVC, MPEG-2, and VC-1 utilize inter-frame prediction coding, also called motion
compensation, as part of the technique for achieving efficient compression of video to produce high quality images at low bit
rates. Inter-frame prediction coding involves reading large numbers of small arrays of pixel data from DRAM and processing
this data to produce approximate values of regions of the current picture from previously decoded pictures.
Memory Accesses for Video Decompression
A very large portion of the DRAM bandwidth required during the decoding process is from the prediction read operations.
The data that needs to be read from DRAM for prediction is dependent on the compressed video stream, and with many
streams the read operations that are required are inherently complex and inefficient. The DRAM controller and the
arrangement of video data in DRAM are optimized to minimize the number of DRAM clock cycles required to decode worst
case compressed video streams.
Various other types of DRAM accesses are required for decoding and displaying digital video, including raster-oriented
bursts, reading and writing macroblocks, and access to small arrays of auxiliary data.
DDR C
LOCK
G
ENERATION
The internal DDR PLL can generate the following frequencies for the DDR memory interface. The output frequency follows
the equation Freq = 3.375 * (N1 divide ratio) * (N2 divide ratio). The default value of this register generates 400 MHz.
