Broadcom BCM7405 General Information Manual Download Page 61 | Manualshive

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2/24/2008 9T6WP

Preliminary Hardware Data Module

BCM7405

06/29/07

Functional Description

Bro a d c o m Co rp o r a ti o n

Document

7405-1HDM00-R

Video and Graphics Display Page 1-47

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CrY0CbY1_8888

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CbY1CrY0_8888

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CbY0CrY1_8888

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8-bit format

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A_4

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A_2

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A_1

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P_8

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Other formats

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A_4

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A_2

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A_1

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P_4

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P_2

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P_1

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P_0

Color Keying and Color Matrix Architecture

Due to the mathematical complexity of the color matrix, this block can only handle one pixel per clock at the maximum rate.
The color keying operation is computationally simple enough to allow multiple pixels but to allow the order selection of when
color keying occurs, it has also been limited to this same one pixel per clock limit.

Color Matrix

The color matrix component allows conversion between different color schemes. To handle color conversion (between
differing formats), a 3 x 4 matrix multiplication is performed. This also allows reordering of components as preferred. For
example, an ARGB ordered data structure could be reordered to RGBA by correctly setting the matrix coefficients. Any
brightness, contrast, or hue adjustments would also be handled within this matrix. For details on the color conversion matrix,
see

“Compositor” on page 1-42

If converting from YUV to YCrCb data, the matrix can add or subtract the 128 value constant.

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Summary of Contents for BCM7405

Page 1: ...2 24 2008 9T6WP PRELIMINARY HARDWARE DATA MODULE BCM7405 7405 1HDM00 R 5300 California Avenue Irvine CA 92617 Phone 949 926 5000 Fax 949 926 5203 06 29 07 General Information...

Page 2: ...is hardware data module including without limitation the Broadcom component s identified herein is not designed intended or certified for use in any military nuclear medical mass transportation aviati...

Page 3: ...1 9 Video Encoder 1 10 Video DACs 1 10 Data Transport Processor 1 11 Overview 1 11 Features 1 11 Functional Overview 1 13 Data Transport I O Connections 1 16 Data Transport Input Bands 1 16 Throughput...

Page 4: ...XVID 1 31 MPEG 1 H 261 H 263 1 31 Features 1 31 Supported Picture Sizes 1 31 Output Data Format 1 31 AVD Block Diagram and Data Flow Description 1 32 Advanced Audio Module 1 33 Features 1 34 Overview...

Page 5: ...Architecture 1 49 Digital Video Decoder ITU R 656 1 50 VBI Decoding 1 50 Analog Video Encoder 1 50 VBI Encoding 1 52 Video DACs 1 53 Digital Video Encoder 1 53 Safe Mode 1 53 Supported Modes 1 54 Sup...

Page 6: ...65 Execution Unit 1 65 Multiply Divide Unit 1 66 Floating Point Unit 1 66 eDSP Extended Instructions 1 67 MIPS16e Application Specific Extension 1 67 Memory Management Unit with TLB 1 67 System Contro...

Page 7: ...ter Interface Operation 1 79 BSC Slave 1 79 BSC Operation 1 79 PWMs 1 80 Timer Counters 1 80 Smart Card Interfaces 1 80 Features 1 81 M Card CPU Interface 1 82 Introduction 1 82 Input and Output Proce...

Page 8: ...t Timing Clock Data Sync Mode 1 152 MPOD Output Timing 1 153 I2S Audio Compressed I2S Output Timing 1 154 SPDIF Audio Output Timing 1 155 DAC Audio Output Timing 1 156 256Fs Audio Clock Output Timing...

Page 9: ...one Crystal Oscillator 1 169 External Components 1 170 SATA Crystal 1 170 Electrical Characteristics 1 171 Absolute Maximum Ratings 1 172 Recommended Operating Conditions 1 172 Thermal Data 1 173 Ther...

Page 10: ...2 24 2008 9T6WP BCM7405 Preliminary Hardware Data Module 06 29 07 Broadcom Corporation Page x Document 7405 1HDM00 R...

Page 11: ...Figure 1 15 Memory Controller Partition 1 60 Figure 1 16 Block Diagram of the CPU 1 65 Figure 1 17 Little and Big Endian Byte Ordering 1 69 Figure 1 18 Flash IR Scheme Example 1 72 Figure 1 19 IR Blas...

Page 12: ...gure 1 41 DAC Audio Output Timing Diagram 1 156 Figure 1 42 256Fs Audio Clock Output Timing Diagram 1 157 Figure 1 43 PCI Interface Timing Diagram 1 158 Figure 1 44 Async Read Timing Diagram 1 159 Fig...

Page 13: ...tion 1 58 Table 1 16 FPU Latency and Repeat Rate 1 67 Table 1 17 Power Estimate 1 93 Table 1 18 Power Configuration Example 1 93 Table 1 19 Pin Descriptions 1 96 Table 1 20 Power On Strap Settings 1 1...

Page 14: ...put at vo_656 Pins 1 166 Table 1 37 Timing for Alternate 656 Output at vi0_656 Pins 1 167 Table 1 38 Timing for Serial Teletext Output at rmx_data1 Pin 1 167 Table 1 39 Electrical Specifications 1 169...

Page 15: ...2 24 2008 9T6WP Preliminary Hardware Data Module BCM7405 06 29 07 Document Overview Broadcom Corporation Document 7405 1HDM00 R Page 1 1 General Information DOCUMENT OVERVIEW Overview 1 2...

Page 16: ...05 does not contain Front End Functions 7405 3HDM0x Data Transport Audio Video and Graphics This document contains information on the following functionality Data Transport Processor Advanced Audio Mo...

Page 17: ...nformation FUNCTIONAL DESCRIPTION Top Level Overview 1 4 Video Data Flow 1 8 Data Transport Processor 1 11 Broadcom Security Processor 1 28 Advanced Video Decoder 1 29 Advanced Audio Module 1 33 Video...

Page 18: ...coder also supports high definition VC 1 Advanced Profile Level 3 Main and Simple Profiles and ATSC compliant MPEG 2 Main Profile at Main and High Levels The BCM7405 has an advanced programmable audio...

Page 19: ...frames sec New tools in the AVC fidelity range extensions 8 x 8 transform and spatial prediction modes Adaptive quantization matrix DivX 3 11 4 1 5 x progressive and interlaced VC 1 advanced profile l...

Page 20: ...ion algorithms standards DVB ARIB and DC2 compliant transport demux with 1DES 3DES DVB Multi2 AES descramblers V 92 capable soft modem with Integrated SiLab Si305X System Side Device Optional five wir...

Page 21: ...4KD MMU and FPU 8K RAC 128K L2 Advanced 2D Graphics Display Engine PCM Audio Engine and DACs Bus Bridge DRAM Controller DMA MCARD SCARD Transport Input x6 Channel 3 4 HDMI SD Video HD SD Video SPDIF C...

Page 22: ...through the HDMI interface Figure 1 2 illustrates this high level data flow Figure 1 2 Video Data Flow Diagram COMPRESSED VIDEO INPUT Compressed video data normally enters the device in the form of MP...

Page 23: ...fast and slow decoding and descrambling and data flow management in the absence of a physical time base associated with the stream as would normally be present in broadcast operation DIGITAL VIDEO DE...

Page 24: ...ed down version of an HD image on the second television output The BCM7405 provides a single user experience that allows for simultaneous outputs of the same content for high definition and standard d...

Page 25: ...rimary PID table for parsing MPEG transport packets Primary PID table entries can be arbitrarily assigned to any of the parser bands The parser bands are processed uniquely even in cases when they use...

Page 26: ...Substitution and PCR correction support for two dual channel remux Interface blocks with a maximum 100 Mbps rate Combines any two transport streams from the available input streams or playback channe...

Page 27: ...rd audio and video interface engine function which supports up to 24 channels Each RAVE channel can be configured as a record channel for PVR or as an AV channel to interface to audio and video decode...

Page 28: ...MF0 TSMF1 Timebase for Timestamp generation MPOD Out MPOD In To MPOD From MPOD Mem to Mem Security AES 1DES 3DES C2 CPRM CPPM CSS DTCP Key table EXT Inputs RMX1 RMX1P RMX0 Mem to Mem I F 0 X C B U F F...

Page 29: ...l Used for the PID Channels that have an associated DMA message buffer All DMA Channels have an associated PID Channel Record Channel Refers to the stream that has been selected for recording This str...

Page 30: ...ptions refer Data Transport in the BCM7405 Programmer s Register Reference Guide The data transport module provides one external parallel transport stream input Input band 4 can be used as either seri...

Page 31: ...ata from PID channels 0 127 may be used by the RAVE record audio and video interface engine or output via the Remux module Common values among all parser bands are processed independently Each PID par...

Page 32: ...ing local timestamp This allows the software to more accurately determine the PCR errors and to determine unmarked PCR discontinuities More robust algorithms can be performed by the host CPU to suppor...

Page 33: ...the previous link list The DMA rate will sustain insertion of every packet being adjacent except at link list read times The insertion modes and rates can be configured dynamically when the module is...

Page 34: ...ost CPU to read The host CPU can always read the latest scrambling control bits for each channel and a per PID status bit signals whether the scrambling bit is valid since the last read NDS ICAM Modul...

Page 35: ...offset For MPEG mode only the SAM filters examine the PSI section header syntax and the filters on address compare with the special mode addresses There is one 40 bit physical address and one multica...

Page 36: ...upts for any of the data available status or error conditions Each of these conditions are individually maskable The interrupt status registers can be read to determine the conditions and written low...

Page 37: ...code locations within the associated record buffer 2 The PTS index entry provides PTS values extracted from the recorded stream 3 The TPIT transport field parser stores transport field index entries F...

Page 38: ...ions of video access units picture start codes and the start of the first row for each access unit The following lists the conditions for storing start codes 1 Start codes are stored in an alternating...

Page 39: ...pt data in any of the following input formats 1 MPEG transport from live or playback source 2 DIRECTV transport from live or playback source 3 PES playback source 4 ES playback source 5 Program Stream...

Page 40: ...ignal is sent out as the sync bit All data is output none is flushed or skipped due to not being in sync as in the TS1 TS2 and PES modes of operation The sync extractor also generates an out of sync r...

Page 41: ...programmed by the host CPU to search for a given PID For MPEG streams each time a PCR is found the 33 bit base and 9 bit extension are captured into a register and the phase compare interrupt is asser...

Page 42: ...and audio These applications can range from single purpose conditional access CA for watching TV only STB to multi purpose copy protection CP for Personal Video Recorder PVR STB and digital right mana...

Page 43: ...ocessing of such a stream has two major components front end processing the conversion of the code stream into fundamental components motion vectors transform coefficients and the like and back end pr...

Page 44: ...40 megabits per second This level supports pictures in the 1920x1088 interlaced format used by HDTV systems at a rate of 60 fields per second VC 1 The AVD module supports VC 1 elementary streams in th...

Page 45: ...o 1920x1088 OUTPUT DATA FORMAT The decoder stores images in a striped format that s designed to optimize two dimensional transfers The images are stored in 4 2 0 format with luminance separate from ch...

Page 46: ...r to generate a BIN representation For CAVLC encoded streams this operation is not necessary Once the outer loop RISC determines that it has enough data to start decoding it passes a structure to the...

Page 47: ...me stamp management and processing PCM data The AIO consists of the FMM one HIFIDAC and audio input output interfaces The main functions include capturing I2 S data mixing and volume control of the pl...

Page 48: ...DIF simultaneously with one stream of decompressed data on the dual stereo DAC outputs Compressed AAC MPEG Layer 1 2 and 3 DTS and Dolby Digital on I2 S output Dynamic Range Compression on all algorit...

Page 49: ...The compressed stream should use only one ring buffer instead of two The SRC block can sample rate convert a stream left and right PCM via a high fidelity SRC or a low fidelity linear interpolator Th...

Page 50: ...o using a new compositor This new compositor allows up to two video surfaces to be combined with a graphical surface frame buffers The blending order of any surface is controlled by software to allow...

Page 51: ...0 p 59 94 480 i 59 94 480 p 59 94 1080 i 50 720 p 50 576 i 50 576 p 50 1080 p 30 1080 p 24 1080 i 60 x x x x x x1 x x1 720 p 60 x x x x x x1 x x1 480 i 60 x x x x x x1 x x1 480 p 60 x x x x x x1 x x1...

Page 52: ...tures Scaling BLT functions ROP operations TOP LEVEL PARTITIONING The graphics and video engine of the BCM7405 is comprised of two major sections the Memory to Memory Compositor and the BVN Figure 1 7...

Page 53: ...c design of the BVN structure Figure 1 8 Video Display Engine Block Diagram M0 Crossbar Crossbar MPEG Feeder Accepts 4 2 0 4 2 2 data supplies 4 2 2 data Video Feeder Accepts 4 2 2 data supplies 4 2 2...

Page 54: ...the stripe width is programmable but feeder supports only 64 bytes stripe width A picture in the AVD format contains two separate arrays one is for luma Y components and the other is for chroma Cb and...

Page 55: ...mpling position Sampling position is maintained internally using two M mod N counters one horizontal and one vertical It is rounded to the nearest 1 256 pixel in both directions In addition sampling p...

Page 56: ...r the current decoded pixels block Creation of a film grain block of pixels Retrieving a block film grain samples from film grain database according to the film grain parameters Scaling those samples...

Page 57: ...ise appears as edges on 8x8 blocks and gives the appearance of a mosaic or tiles Mosquito Noise refers to the MPEG artifacts caused by quantization of high frequency components It is also called ringi...

Page 58: ...tion a k a copy BLT More complex operations include ROP blend and or scale options Features Picture Size Up to 8191 pixels per line and 8191 lines per picture for both input and output Pixel Format Ac...

Page 59: ...line averaging filter two of these line stores would be required totaling 128 Kbits By using a vertical stripping algorithm eight line stores each holding 128 32 bit pixels would only take 32 Kbits wo...

Page 60: ...support CLUT and palette formats The feeder is responsible for supplying the appropriate amount of information to the downstream modules For example if an A0 format constant color and alpha is request...

Page 61: ...ls but to allow the order selection of when color keying occurs it has also been limited to this same one pixel per clock limit Color Matrix The color matrix component allows conversion between differ...

Page 62: ...AYCrCb8888 The alpha and color values should have different blend functions but both are based on the A B C D E formula The compositor has three effective inputs for each of the letters A B C D and E...

Page 63: ...ses Common uses of the ROP function are to handle screen door blends and fades Software has to handle any initial offset in the 8 x 8 bit map registers This can be accomplished by simply reloading the...

Page 64: ...module that takes a series of video inputs from multiple sources inserts fly backs hblank and vblank formats the signal into multiple valid output video standards and additionally handles the inserti...

Page 65: ...ming Mode North America Set top box Broadcom Internal Spec 1716x525 7 720x576i 50Hz SECAM ITU 470 6 1728x625 8 720x576i 50 Hz PAL ITU R BT 470 6 1728X625 9 720x576i 50 Hz PAL Macrovision AGC Macrovisi...

Page 66: ...etext NABTS WSS CGMS A Gemstar SCTE20 21 and AMOL I II VBI Encoding Table 1 9 VBI Encoding Mnemonic Standard Output format Resolution Direct Encode Retrieve from Memory Sampled Graphics BVID IEC 61880...

Page 67: ...cryption block and related control logic The BCM7405 also implements the master control of HDCP authentication and revocation process Safe Mode Safe mode is a required display mode for DVI 1 0 complia...

Page 68: ...DMI DVI 720p_50hz EIA CEA 861 B 1650x750 8 1920x1080i 50 Hz HDMI DVI 1125i_50hz EIA CEA 861 B 2200x1125 9 640x480 60 Hz DVI Safe Mode EIA CEA 861 A 800X525 10 800x600 60 Hz SVGA VESA dmt09 1056x628 11...

Page 69: ...that it can support Table 1 12 DVI PC Scan Clock Rates Mode of Operation Frequency Frequency Ratio from 27 MHz Ratio from 25 MHz Comments Consumer Electronics Display Modes 25 175 25 200 14 15 Safe m...

Page 70: ...M and N Supports monaural audio formats used worldwide including NTSC and most PAL variants Supports stereo encoding and transmission for BTSC and NICAM standards For BTSC this includes generation of...

Page 71: ...of baseband composite video signal and FM modulated audio carrier and optional NICAM DQPSK carrier to a programmable frequency that can be chosen from 0 to 75 MHz This includes NTSC channels 3 and 4...

Page 72: ...pair produced by a stereophonic source in MONO usage mode LEFT and RIGHT can both be replaced by the same monaural source if no stereo source is available MONO refers to monaural source SAP refers to...

Page 73: ...DDR2 interface 4 One 32 bit DDR2 interface and one 16 bit DDR2 interface 5 One 16 bit DDR2 interface and another 16 bit DDR2 interface Assuming that in Modes 4 and 5 the two controllers are independen...

Page 74: ...ory Controller Document 7405 1HDM00 R Figure 1 15 Memory Controller Partition Word 0 Word 1 Word 2 Word 3 Addr Cntrl 1 Addr Cntrl 2 64 BIT DDR2 IOB UF Memory Controller Core 1 Memory Controller Core 2...

Page 75: ...ing in 64 MB 32Mx16 resulting in 128 MB 64Mx16 resulting in 256 MB 128Mx16 resulting in 512MB For UMA 16 bit memory controller supports these single chip configurations 16Mx16 resulting in 32 MB 32Mx1...

Page 76: ...re complex advanced formats Digital Video Compression Standards Video compression standards such as AVC MPEG 2 and VC 1 utilize inter frame prediction coding also called motion compensation as part of...

Page 77: ...tions IEEE 754 standard floating point unit supporting single precision and double precision MIPS16e application specific extension Multiply accumulate instructions MADD MADDU MSUB MSUBU Targeted mult...

Page 78: ...ta cache to be continuously accessed and stored L2 cache holding lines displaced from the instruction and data caches 8 way set associative with a capacity of 128 KB a line size of 64 bytes and LRU re...

Page 79: ...bypassed to minimize latency in the six stage pipeline The execution unit includes Branch unit for branch resolution and next instruction calculation MIPS32 and MIPS16e instruction decoding units ALU...

Page 80: ...mplements an additional multiply instruction MUL which specifies that the lower 32 bits of the multiply result be placed in a general purpose register instead of the LO register this eliminates the ne...

Page 81: ...form multiple loads and stores at subroutine calls and returns A 16 bit program is invoked as a subroutine and can be executed with other 32 bit programs in one application Each TP can execute a MIPS1...

Page 82: ...a CMT CPU local and shared CP0 registers Each TP can access all the shared CP0 registers but the set of local registers to a TP allows the TP to perform all the execution exceptions INSTRUCTION CACHE...

Page 83: ...C control registers in the core register space for an application to set up and control the RAC operations There are replicated RAC control fields for each TP to set up the prefetching options indepen...

Page 84: ...the CPU provides a non intrusive hardware debugging support of two of each of instruction data and data value hardware breakpoints The hardware instruction breakpoints can be configured to generate a...

Page 85: ...e keypad controller notifies the microcontroller whenever it detects that a key has pressed via an interrupt When the processor responds to the interrupt the scan code of the key s detected is reporte...

Page 86: ...ogic is a single bit pulse stream This stream is then converted to infrared light by an external IR emitter The IR blaster provides support for two types of IR transmission IR Flash This modulation sc...

Page 87: ...ger then the last carrier pulse is truncated In other words the quantity below must be an integer or the last carrier pulse is truncated modCnt x modPrescale carrHi carrLO x carrPrescale The sequence...

Page 88: ...ceiver with External Components The digital front end processes the digitally sampled IF signal as shown in Figure 1 21 on page 1 75 The digitally sampled IF signal is mixed with a 10 7 MHz carrier fr...

Page 89: ...f the interrupt is not enabled the interrupting condition may be polled in KBD_STATUS irq The received data packet can be found in KBD_DATA0 4 registers Details of the register definitions can be foun...

Page 90: ...tarts the sequence This is followed by seven or eight data bits 0 or one parity bit and one stop bit a High for 1 bit interval The start bit for a data sequence may immediately follow the stop bit of...

Page 91: ...rent data and status The Receive Data Available RDA bit in the UART_RCVSTAT register status is asserted whenever the FIFO has data GENERIC I O PORT CONTROLLER The BCM7405 contains 59 bits of general p...

Page 92: ...Length The programmable length simplifies interfacing with serial peripherals that require different data lengths The number of bits in the transfer is programmable from eight to sixteen bits inclusi...

Page 93: ...t state control are not supported The BSC interface consists of the serial data SDA and serial clock SCL signals which can control a large number of devices on a common bus The addressing of the diffe...

Page 94: ...M output is connected directly to the most significant bit of the accumulator During normal operation the PWM output reflects the state of the accumulator s carry out position Figure 1 24 Variable Fre...

Page 95: ...ng or monitoring events based on the Smart Card Clock or Elementary Time Units Flow control monitoring and support Automatic block ready interrupt by extracting LEN field Automatic insertion and check...

Page 96: ...the MCIF and SDO is the data coming out When the start of a packet occurs the first byte is defined as the interface query byte which includes the interface flags After the interface query byte the pa...

Page 97: ...bits in the Interrupt Status Register MRPKT This is set at the end of each packet read TX_DONE This is set once the whole packet has been transferred The MCIF clears the GO bit at this time Input From...

Page 98: ...a modified PCI master with special request and grant handshaking If an external PCI arbiter is selected the special EBI request grant pair maps to the PCI GNT2b REQ2b pins The EBI is an external bus i...

Page 99: ...I_ADDR 23 PCI_FRAMEb EBI Address EBI_TSb EBI_DSb EBI_WEb 1 0 EBI_RDb PCI_AD 31 16 EBI_ADDR 15 0 PCI_CBE 3 0 EBI_ADDR 19 16 EBI_CSb PCI_STOPb EBI_ADDR 22 EBI Address EBI Data PCI Addr PCI Addr PCI CMD...

Page 100: ...I_ADDR 23 PCI_FRAMEb EBI Address EBI_RWb EBI_DSb EBI_WEb 1 0 EBI_RDb PCI_AD 31 16 EBI_ADDR 15 0 PCI_CBE 3 0 EBI_ADDR 19 16 EBI_CSb PCI_STOPb EBI_ADDR 22 EBI Address EBI Data PCI Addr PCI Addr PCI CMD...

Page 101: ...ADDR 23 PCI_FRAMEb EBI Address EBI_RWb EBI_DSb EBI_RDb 1 0 EBI_WEb 1 0 PCI_AD 31 16 EBI_ADDR 15 0 PCI_CBE 3 0 EBI_ADDR 19 16 EBI_CSb PCI_STOPb EBI_ADDR 22 EBI Address PCI Addr PCI Addr PCI CMD PCI Dat...

Page 102: ...ADDR 23 PCI_FRAMEb EBI Address EBI_TSb EBI_DSb EBI_RDb 1 0 EBI_WEb 1 0 PCI_AD 31 16 EBI_ADDR 15 0 PCI_CBE 3 0 EBI_ADDR 19 16 EBI_CSb PCI_STOPb EBI_ADDR 22 EBI Address PCI Addr PCI Addr PCI CMD PCI Dat...

Page 103: ...AC provides the control and protocol functions necessary for the transmission and reception of 802 3 data streams During transmission packet data is removed from the transmit FIFO framed with preamble...

Page 104: ...ansceiver is able to operate at a transfer rate of 480 Mbps The device controller communicates at a rate of 480 Mbps A third USB 2 0 host client port is available and is independent and private with r...

Page 105: ...I bus and to allow an external controller to access the peripherals and memory associated with the BCM7405 Software running on the internal MIPS32 processor can allow the BCM7405 to act as a South bri...

Page 106: ...est modes These tests can be self checking or they are compared to golden test patterns Test Buses During Test mode the core under test has various internal signals routed to external pins to improve...

Page 107: ...employ the setting in Table 1 18 POWER MODES FOR DDR DRAM MEMORY CONTROLLER It is possible to configure each of the DDR DRAM Memory Controllers to go into a Self refresh mode to further reduce the po...

Page 108: ...ENCE The BCM7405 can accept any of the power rail sequence but all should be stable within 20 ms from any power rail raising past 50 mV The RESETb signal should be held active for 75 ms after the last...

Page 109: ...ardware Data Module BCM7405 06 29 07 Hardware Signal Descriptions Broadcom Corporation Document 7405 1HDM00 R Page 1 95 General Information HARDWARE SIGNAL DESCRIPTIONS Pin Definition Notations 1 96 P...

Page 110: ...up resistor Ext PU External pull up required Ext PD External pull down required S O Output signal with strap Input Table 1 19 Pin Descriptions of Pins Orcad Schematic Block Label I O Res Tol V Drv mA...

Page 111: ...rface VDAC1_VRE G AI 3 3 D25 Video DAC voltage regulator 1 11 UHF Video HDMI RFM AUDIO VDAC0_AVD D33 APWR 3 3 C26 Video DAC isolated supply 3 3V 1 11 UHF Video HDMI RFM AUDIO VDAC1_AVD D33 APWR 1 2 D2...

Page 112: ...h LED_LS_4 EXT_GFX_08 HDMI Output 17 1 7 Digital Video HDMI_0_P AO 3 3 A19 Channel 0 data positive 1 7 Digital Video HDMI_0_N AO 3 3 B19 Channel 0 data negative 1 7 Digital Video HDMI_1_P AO 3 3 A18 C...

Page 113: ...UDIO RFM_AVDD1 P2 APWR 1 2 D27 RF modulator digital 1 2 volt power supply 1 11 UHF Video HDMI RFM AUDIO RFM_AVSS_0 AGND GND E28 RF modulator analog ground 1 11 UHF Video HDMI RFM AUDIO RFM_AVSS_1 AGND...

Page 114: ...DMI RFM AUDIO DDR_BVDD1 I O Ext PU SSTL _18 C6 DDR 1 2 V analog voltage 1 11 UHF Video HDMI RFM AUDIO DDR_BVSS0 I O Ext PU SSTL _18 AK6 DDR analog ground 1 11 UHF Video HDMI RFM AUDIO DDR_BVSS1 I O Ex...

Page 115: ...bit lane 3 1 14 64 Bit DDR2 SDRAM DDR01_A00 I O Ext PU SSTL _18 AE5 Shared DDR DRAM Address Bus for 16 bit lane 0 and 1 1 14 64 Bit DDR2 SDRAM DDR01_A01 I O Ext PU SSTL _18 AF2 Shared DDR DRAM Addres...

Page 116: ...ress Bus for 16 bit lane 1 1 14 64 Bit DDR2 SDRAM DDR23_A00 I O Ext PU SSTL _18 J5 Shared DDR DRAM Address Bus for 16 bit lane 2 and 3 1 14 64 Bit DDR2 SDRAM DDR23_A01 I O Ext PU SSTL _18 H2 Shared DD...

Page 117: ...xt PU SSTL _18 AE2 DDR DRAM Bank Address for 16 bit lane 0 and 1 1 14 64 Bit DDR2 SDRAM DDR01_BA1 I O Ext PU SSTL _18 AD4 DDR DRAM Bank Address for 16 bit lane 2 and 3 1 14 64 Bit DDR2 SDRAM DDR01_BA2...

Page 118: ...14 64 Bit DDR2 SDRAM DDR0_DQ14 I O Ext PU SSTL _18 AP2 DDR DRAM Data bus for 16 bit lane 0 1 14 64 Bit DDR2 SDRAM DDR0_DQ15 I O Ext PU SSTL _18 AK4 DDR DRAM Data bus for 16 bit lane 0 1 14 64 Bit DDR2...

Page 119: ...14 64 Bit DDR2 SDRAM DDR2_DQ05 I O Ext PU SSTL _18 N5 DDR DRAM Data bus for 16 bit lane 2 1 14 64 Bit DDR2 SDRAM DDR2_DQ06 I O Ext PU SSTL _18 U4 DDR DRAM Data bus for 16 bit lane 2 1 14 64 Bit DDR2 S...

Page 120: ...1 14 64 Bit DDR2 SDRAM DDR3_DQ12 I O Ext PU SSTL _18 A4 DDR DRAM Data bus for 16 bit lane 3 1 14 64 Bit DDR2 SDRAM DDR3_DQ13 I O Ext PU SSTL _18 B1 DDR DRAM Data bus for 16 bit lane 3 1 14 64 Bit DDR2...

Page 121: ...4 DDR DRAM Data Strobe for 16 bit lane 2 1 14 64 Bit DDR2 SDRAM DDR2_DQS1b I O Ext PU SSTL _18 R5 DDR DRAM Data Strobe low active for 16 bit lane 2 1 14 64 Bit DDR2 SDRAM DDR3_DQS0 I O Ext PU SSTL _18...

Page 122: ...PCI Address Data bus Shared with EBI_DATA10 1 1 PCI Bus EBI PCI_AD11 I O Ext PU 3 3 AK22 PCI Address Data bus Shared with EBI_DATA11 1 1 PCI Bus EBI PCI_AD12 I O Ext PU 3 3 AL21 PCI Address Data bus...

Page 123: ...ed with EBI_ADDR16 1 1 PCI Bus EBI PCI_CBE01 I O Ext PU 3 3 AM23 PCI command byte enable Shared with EBI_ADDR17 1 1 PCI Bus EBI PCI_CBE02 I O Ext PU 3 3 AM25 PCI command byte enable Shared with EBI_AD...

Page 124: ...Shared with NAND FLASH R B control 1 2 Extended Bus Interface Reset In Out EBI_ADDR24 S O 3 3 8 AN19 EBI Address bus 1 2 Extended Bus Interface Reset In Out EBI_ADDR25 S O 3 3 8 AL16 EBI Address bus...

Page 125: ...supply input 1 11 UHF Video HDMI RFM AUDIO UHF_AVDD25 APWR 2 5 D31 UHF 2 5V power supply input 1 11 UHF Video HDMI RFM AUDIO UHF_AVDD33 APWR 3 3 C31 UHF 3 3V power supply input 1 11 UHF Video HDMI RF...

Page 126: ...red with Observe PLL 1 15 Ethernet USB SATA USB1_DP I O PD 3 3 A12 D signal of USB port 2 Transceiver 1 15 Ethernet USB SATA USB1_DN I O PD 3 3 B12 D signal of USB port 2 Transceiver 1 15 Ethernet USB...

Page 127: ...g Ground Ethernet 12 1 15 Ethernet USB SATA EPHY_VREF AI 2 5 E13 Ethernet internal voltage reference 1 15 Ethernet USB SATA EPHY_RDAC AI 2 5 E14 Ethernet DAC Bias Resistor 1 15 Ethernet USB SATA EPHY_...

Page 128: ...er for channel 2 1 15 Ethernet USB SATA SATA_TXDN2 AO 1 2 J32 Differential transmitter for channel 2 1 11 UHF Video HDMI RFM AUDIO SATA_AVDD1 2_0 APWR 1 2 H31 Receiver 1 2 analog 1 2 volt power 1 11 U...

Page 129: ...Generic I O port Shared with ENET_LINK ENET_ACTIVITY Ext IRQb_14 1 16 GPIO GPIO_002 STI O PD 3 3 8 AB34 Generic I O port Shared with MII_RX_CLK Ext IRQb_0 EXT_GFX_09 1 16 GPIO GPIO_003 STI O PD 3 3 8...

Page 130: ...D 3 3 8 W34 Generic I O port Shared with MII_TXD_02 UART_CTS_2 EXT_GFX_20 TTX0_REQ Ext IRQb_3 1 16 GPIO GPIO_014 STI O PD 3 3 8 W33 Generic I O port Shared with MII_TXD_03 UART_RTS_2 EXT_GFX_21 TTX0_D...

Page 131: ...K Ext IRQb_10 1 16 GPIO GPIO_025 STI O PD 3 3 8 L31 Generic I O port Shared with CHIP2POD_SCLK SPI_M_SCK EBI_ADDR_01 1 16 GPIO GPIO_026 STI O PD 3 3 8 L30 Generic I O port Shared with POD2CHIP_SDI SPI...

Page 132: ..._SYNC4 1 16 GPIO GPIO_038 STI O PD 3 3 8 P31 Generic I O port Shared with POD2CHIP_MDI7 PPKT_DATA7 UART_RXD_2 1 16 GPIO GPIO_039 STI O PD 3 3 8 M30 Generic I O port Shared with POD2CHIP_MICLK PPKT_CLK...

Page 133: ...Shared with CHIP2POD_MDO6 RMXP_DATA6 EBI_ADDR_24 SC_RST_1 CODEC_FSYNCb 1 16 GPIO GPIO_049 STI O ExtPU PD 5 8 R31 Generic I O port Shared with CHIP2POD_MDO7 RMXP_DATA7 EBI_ADDR_25 SC_PRES_1 CODEC_SDO 1...

Page 134: ...red with PKT_VALID1 VI_656_3 UART_RTS_0 Ext IRQb_6 TTX0_DATA 1 16 GPIO GPIO_059 STI O PD 3 3 8 AB31 Generic I O port Shared with PKT_VALID2 VI_656_4 UART_CTS_1 Ext IRQb_7 VEC_VSYNC_0 1 16 GPIO GPIO_06...

Page 135: ...AH32 Generic I O port Shared with PKT_DATA3 EXT_GFX_31 1 22 GPIO GPIO_073 STI O PD 3 3 8 AH31 Generic I O port Shared with PKT_DATA4 EXT_GFX_IN_CLK VI_656_2 UART_CTS_2 1 22 GPIO GPIO_074 STI O PD 3 3...

Page 136: ...3 8 AL11 Generic I O port Shared with LED_KD_0 MII_TX_CLK DVO0_DE 1 22 GPIO GPIO_087 STI O PU 3 3 8 AK11 Generic I O port Shared with LED_KD_1 MII_TX_EN DVO0_CLK_N 1 22 GPIO GPIO_088 STI O PU 3 3 8 A...

Page 137: ..._02 DVO0_10 1 22 GPIO GPIO_101 STI O PD 3 3 8 AK7 Generic I O port Shared with LED_LD_6 MII_RXD_03 DVO0_11 1 22 GPIO GPIO_102 STI O PD 3 3 8 AN8 Generic I O port Shared with LED_LD_7 MII_RX_ER DVO0_CL...

Page 138: ...GPIO SGPIO_02 STI OD Ext PU 5 8 B16 Generic I O port Shared with BSC_M1_SCL 1 22 GPIO SGPIO_03 STI OD Ext PU 5 8 D17 Generic I O port Shared with BSC_M1_SDA 1 22 GPIO SGPIO_04 STI OD Ext PU 5 8 V33 Ge...

Page 139: ..._1 APWR 1 2 G31 PLL Power Supply 1 2V 5 5 1 12 Clocks CLK27_OUT O 5 12 AL13 27 MHz output Shared with 33 MHz clock output 1 12 Clocks VCXO27A O 3 3 8 AK14 27 MHz VXCO output clock EJTAG 7 1 8 EJTAG Br...

Page 140: ...l Power Supply 3 3V I O 10 1 17 D3 3V VDDO V V 3 3 AJ25 Digital Power Supply 3 3V I O 10 1 17 D3 3V VDDO V V 3 3 AJ21 Digital Power Supply 3 3V I O 10 1 17 D3 3V VDDO V V 3 3 AG29 Digital Power Supply...

Page 141: ...17 D3 3V VDDO V V 3 3 AJ19 Digital Power Supply 3 3V I O 10 1 17 D3 3V VDDO V V 3 3 AJ23 Digital Power Supply 3 3V I O 10 1 17 D3 3V VDDO V V 3 3 U29 Digital Power Supply 3 3V I O 10 1 17 D3 3V VDDO V...

Page 142: ...Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 AD18 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 AD19 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 AD20 Digital Power Supply 1...

Page 143: ...V 1 2 Y12 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 AB12 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 AA11 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 T11 Digit...

Page 144: ...1 2 U10 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 V10 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 W10 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 Y10 Digital P...

Page 145: ...V 1 2 N10 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 R10 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 P10 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 R11 Digital...

Page 146: ...D1 2V VDDC V V 1 2 K12 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 K10 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1 2 K11 Digital Power Supply 1 2V core 5 1 20 D1 2V VDDC V V 1...

Page 147: ...al Power Supply DDR0 1 8V I O 5 1 18 DDR2 1 8V DDRV V V 1 8 AF1 Digital Power Supply DDR0 1 8V I O 5 1 18 DDR2 1 8V DDRV V V 1 8 C1 Digital Power Supply DDR0 1 8V I O 5 1 18 DDR2 1 8V DDRV V V 1 8 AM1...

Page 148: ...gital Ground 1 21 DGND AGND DVSS G G P17 Digital Ground 1 21 DGND AGND DVSS G G P18 Digital Ground 1 21 DGND AGND DVSS G G P19 Digital Ground 1 21 DGND AGND DVSS G G P20 Digital Ground 1 21 DGND AGND...

Page 149: ...d 1 21 DGND AGND DVSS G G W18 Digital Ground 1 21 DGND AGND DVSS G G W19 Digital Ground 1 21 DGND AGND DVSS G G W20 Digital Ground 1 21 DGND AGND DVSS G G W21 Digital Ground 1 21 DGND AGND DVSS G G Y1...

Page 150: ...d 1 21 DGND AGND DVSS G G P13 Digital Ground 1 21 DGND AGND DVSS G G R13 Digital Ground 1 21 DGND AGND DVSS G G T13 Digital Ground 1 21 DGND AGND DVSS G G U13 Digital Ground 1 21 DGND AGND DVSS G G V1...

Page 151: ...round 1 21 DGND AGND DVSS G G R34 Digital Ground 1 21 DGND AGND DVSS G G AD34 Digital Ground 1 21 DGND AGND DVSS G G AD6 Digital Ground 1 21 DGND AGND DVSS G G AD7 Digital Ground 1 21 DGND AGND DVSS G...

Page 152: ...l Ground 1 21 DGND AGND DVSS G G AF29 Digital Ground 1 21 DGND AGND DVSS G G AC28 Digital Ground 1 21 DGND AGND DVSS G G AB28 Digital Ground 1 21 DGND AGND DVSS G G AB29 Digital Ground 1 21 DGND AGND...

Page 153: ...G N24 Analog Ground 1 21 DGND AGND UHF_AVSS G G P23 Analog Ground 1 21 DGND AGND UHF_AVSS G G H28 Analog Ground 1 21 DGND AGND UHF_AVSS G G G29 Analog Ground 1 21 DGND AGND UHF_AVSS G G N23 Analog Gro...

Page 154: ...GND HDMI_AVSS G G L17 Analog Ground 1 21 DGND AGND HDMI_AVSS G G L18 Analog Ground 1 21 DGND AGND HDMI_AVSS G G M18 Analog Ground 1 21 DGND AGND HDMI_AVSS G G F17 Analog Ground 1 21 DGND AGND HDMI_AVS...

Page 155: ...USB_AVSS G G N16 Analog Ground 1 21 DGND AGND PLL_AVSS G G P25 Analog Ground 1 21 DGND AGND PLL_AVSS G G K28 Analog Ground 1 21 DGND AGND SATA_AVSS G G M29 Analog Ground 1 21 DGND AGND SATA_AVSS G G K...

Page 156: ...lated Balls 1 DEPOP AC34 Depopulated Balls 1 DEPOP U34 Depopulated Balls 1 DEPOP P34 Depopulated Balls 1 DEPOP L34 Depopulated Balls 1 DEPOP H34 Depopulated Balls 1 DEPOP E34 Depopulated Balls 1 DEPOP...

Page 157: ...20 Depopulated Balls 1 DEPOP AF21 Depopulated Balls 1 DEPOP AG21 Depopulated Balls 1 DEPOP AF22 Depopulated Balls 1 DEPOP AG22 Depopulated Balls 1 DEPOP AF23 Depopulated Balls 1 DEPOP AG23 Depopulated...

Page 158: ...ls 1 DEPOP AB9 Depopulated Balls 1 DEPOP AC8 Depopulated Balls 1 DEPOP AC9 Depopulated Balls 1 DEPOP AD8 Depopulated Balls 1 DEPOP AD9 Depopulated Balls 1 DEPOP AE8 Depopulated Balls 1 DEPOP AE9 Depop...

Page 159: ...populated Balls 1 DEPOP T26 Depopulated Balls 1 DEPOP R27 Depopulated Balls 1 DEPOP U26 Depopulated Balls 1 DEPOP H11 Depopulated Balls 1 DEPOP H12 Depopulated Balls 1 DEPOP H13 Depopulated Balls 1 DE...

Page 160: ...lls 1 DEPOP H26 Depopulated Balls 1 DEPOP J24 Depopulated Balls 1 DEPOP H27 Depopulated Balls 1 DEPOP J25 Depopulated Balls 1 DEPOP J26 Depopulated Balls 1 DEPOP K26 Depopulated Balls 1 DEPOP J27 Depo...

Page 161: ...ported by BCM7405 strap_ddr_config_1 RMX_DATA0 0 strap_ddr_config_2 USB1_PWRON 0 strap_ddr0_device_ config_0 00 16Mx16 bit device on MEMC0 01 32Mx16 bit device on MEMC0 10 64Mx16 bit device on MEMC0 1...

Page 162: ...al MPI arbiter EBI_WE0b 0 Per system configuration strap_CPU_freq_0 0 297 MHz 1 324 MHz 2 351 MHz default 3 378 MHz 4 405 MHz 5 432 MHz 6 459 MHz 7 148 5 MHz 297 divided by 2 EBI_ADDR25 0 Per system c...

Page 163: ...CTERISTICS Data Transport Input Timing 1 150 MPOD Input Timing 1 151 Data Transport Output Timing 1 152 MPOD Output Timing 1 153 I2S Audio Compressed I2S Output Timing 1 154 SPDIF Audio Output Timing...

Page 164: ...ters Description Symbol Min Max Units IB_CLK frequency Fs 100 MHz IB_CLK rise time1 Trise 2 ns IB_CLK fall time1 Tfall 2 ns IB_DATA IB_SYNC Setup Time to IB_CLK active edge rising or falling 2 Tsu 4 n...

Page 165: ...MPOD_CLK fall time1 Tfall 2 ns i_MPOD_DATA i_MPOD_SYNC Setup Time to i_MPOD_CLK active edge rising or falling 2 Tsu 3 ns i_MPOD_DATA i_MPOD_SYNC Hold Time from i_MPOD_CLK active edge rising or falling...

Page 166: ...Description Symbol Min Max Units RMX clock frequency4 F 81 MHz RMX clock rise time1 2 4 Trise 2 ns RMX clock fall time1 2 4 Tfall 2 ns RMX_DATA RMX_SYNC Output Delay from active clock edge1 3 4 Tdo hs...

Page 167: ...clock rise time1 2 Trise 2 ns o_MPOD_CLK clock fall time1 2 Tfall 2 ns o_MPOD_DATA o_MPOD_SYNC Setup Time to o_MPOD_CLK active edge rising and falling 3 Tsu 3 ns o_MPOD_DATA o_MPOD_SYNC Hold Time to o...

Page 168: ...Timing Parameters Description Symbol Min Typical Max Units edge of sclk to changing lr clock clk_lr 4 4 ns edge of sclk to changing data clk_d 4 4 ns sclk duty cycle sclk_dc 50 sclk period for Fs 96...

Page 169: ...udio Output Timing Diagram Table 1 26 SPDIF Audio Output Timing Parameters Description Symbol Min Typical Max Units Unit Interval for Fs 96 kHz UI_96 81 ns Unit Interval for Fs 48 kHz UI_48 163 ns Uni...

Page 170: ...acteristics 06 29 07 Broadcom Corporation Page 1 156 DAC Audio Output Timing Document 7405 1HDM00 R DAC AUDIO OUTPUT TIMING Figure 1 41 DAC Audio Output Timing Diagram Table 1 27 DAC Audio Output Timi...

Page 171: ...ing Parameters Description Symbol Min Typical Max Units 256Fs_CLK period for Fs 96 kHz Tp_96kHz 40 69 ns 256Fs_CLK frequency for Fs 96 kHz F_96kHz 24 576 MHz 256Fs_CLK period for Fs 48 kHz Tp_48kHz 81...

Page 172: ...Signal Valid Delay buses signals1 2 Tval 2 11 ns PCI CLK to Signal Valid Delay point to point signals1 2 Tval ptp 2 12 ns Float to Active Delay1 2 Ton 2 ns Float to Float Delay1 2 Toff 28 ns Input Set...

Page 173: ...EBI_ADDR 25 0 or EBI_TSIZE 1 0 valid t1 3 13 5 ns Delay time EBI_CLK rising to EBI_CSb n low or high CSHold 0 t2 3 13 5 ns Delay time EBI_CLK falling to EBI_CSb n low or high CSHold 1 t3 3 13 5 ns De...

Page 174: ...1 31 Async Write Timing Parameters Description Symbol Min Max Units Delay time EBI_CLK rising to EBI_DATA 15 0 valid t14 3 11 ns Delay time EBI_CLK rising to EBI_WEb 1 0 or EBI_DSb low or high t15 3...

Page 175: ...lay time EBI_CLK rising to EBI_TSb low or high t2 3 13 ns Delay time EBI_CLK rising to EBI_CSb n low or high CSHold 0 t3 3 13 5 ns Delay time EBI_CLK falling to EBI_CSb n low or high CSHold 1 t4 3 13...

Page 176: ...Timing Diagram Table 1 33 Synchronous Write Timing Parameters Description Symbol Min Max Units Delay time EBI_CLK rising to EBI_DATA 15 0 changing t12 3 11 ns Note Load is 35 pF for all EBI pins The...

Page 177: ...acteristics Broadcom Corporation Document 7405 1HDM00 R DDR Interface Timing Page 1 163 DDR INTERFACE TIMING Figure 1 48 Write Cycle Timing Figure 1 49 Read Cycle Timing CLK CLKb COMMAND ADRS BSx Ts T...

Page 178: ...time w r t clk Ts 1 8 Addr 12 0 output setup time w r t clk Ts 1 9 BA output setup time w r t clk Ts 1 10 RASb output hold time w r t clk Th 1 11 CASb output hold time w r t clk Th 1 12 WEb output hol...

Page 179: ...DVO Page 1 165 HDMI AND DVO Figure 1 50 Clock to Data Timing The configuration values used to adjust the skew settings are all in the HDMI_MISC_CONTROL registers Refer to the BCM7038 Programmer s Reg...

Page 180: ...ccurs midway between data transitions Clock period T 37 ns Clock pulse width t 18 5 ns Data timing sending end td 18 5 3 ns based on the ITU R_BT656 4 specification TIMING FOR ITU656 OUTPUT AT VO_656...

Page 181: ...lock signal occurring midway between data transitions Clock period T 37 ns Clock pulse width t 18 5 ns Data timing sending end td 18 5 3 ns TIMING FOR SERIAL TELETEXT OUTPUT AT RMX_DATA1 PIN Table 1 3...

Page 182: ...BCM7405 Preliminary Hardware Data Module Crystal Requirements 06 29 07 Broadcom Corporation Page 1 168 ITU656 Output Timing Document 7405 1HDM00 R General Information CRYSTAL REQUIREMENTS Crystal Req...

Page 183: ...a 54 MHz crystal operating at the third overtone to generate the internal clock required for the BCM7405 Table 1 39 Electrical Specifications Parameter Symbol Comment Min Typ Max Unit Operating Condit...

Page 184: ...operation of the SATA core if this core is not required for a particular application this crystal does not need to be installed Example Vendor Ecliptek Part Number for SATA crystal E13C4D1F 100MHz Ta...

Page 185: ...ware Data Module BCM7405 06 29 07 Electrical Characteristics Broadcom Corporation Document 7405 1HDM00 R Page 1 171 General Information ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings 1 172 Recomm...

Page 186: ...onal operation is not guaranteed under these conditions Operation at absolute maximum conditions for extended periods may adversely affect long term reliability of the device Table 1 42 Recommended Op...

Page 187: ...2 24 2008 9T6WP Preliminary Hardware Data Module BCM7405 06 29 07 Thermal Data Broadcom Corporation Document 7405 1HDM00 R Page 1 173 General Information THERMAL DATA Thermal Data 1 174...

Page 188: ...Board Device power dissipation P W 6 3 Ambient air temperature TA C 55 JA in still air C W 11 19 JB C W 3 84 JC C W 3 98 2s2p board no extHS Package Thermal Performance Data Air Velocity TJ_max TC_ma...

Page 189: ...9T6WP Preliminary Hardware Data Module BCM7405 06 29 07 Mechanical Characteristics Broadcom Corporation Document 7405 1HDM00 R Page 1 175 General Information MECHANICAL CHARACTERISTICS Mechanical Draw...

Page 190: ...M7405 Preliminary Hardware Data Module Mechanical Characteristics 06 29 07 Broadcom Corporation Page 1 176 Mechanical Drawings Document 7405 1HDM00 R MECHANICAL DRAWINGS Figure 1 54 976 FCBGA HS Packa...

Page 191: ...9T6WP Preliminary Hardware Data Module BCM7405 06 29 07 Mechanical Characteristics Broadcom Corporation Document 7405 1HDM00 R Mechanical Drawings Page 1 177 Figure 1 55 976 FCBGA HS Package Without...

Page 192: ...2 24 2008 9T6WP BCM7405 Preliminary Hardware Data Module Mechanical Characteristics 06 29 07 Broadcom Corporation Page 1 178 Mechanical Drawings Document 7405 1HDM00 R...

Page 193: ...2008 9T6WP Preliminary Hardware Data Module BCM7405 06 29 07 Ordering Information Broadcom Corporation Document 7405 1HDM00 R Page 1 179 General Information ORDERING INFORMATION Ordering Information 1...

Page 194: ...ished by Broadcom Corporation is believed to be accurate and reliable However Broadcom Corporation does not assume any liability arising out of the application or use of this information nor the appli...

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