2/24/2008 9T6WP
Preliminary Hardware Data Module
BCM7405
06/29/07
Functional Description
Bro a d c o m Co rp o r a ti o n
Document
7405-1HDM00-R
Memory Controller Page 1-61
DRAM P
HYSICAL
L
AYER
C
ONTROLLER
The DRAM controller in the BCM7405 has a default DRAM clock rate of 400 MHz and is provided on-chip. Other on-chip
frequencies are supported, and externally supplied DRAM clock can also be used. The DRAM controller only supports DDR2
memory (x16 devices). DRAM controller state machine operation includes specialized transactions for video macro-block
prediction reads and is optimized to maximize the data efficiency.
Memory Configurations Supported
For UMA-64 bit mode, DDR memory controller supports these four-chip configurations in full 64-bit mode.
•
16Mx16 resulting in 128 MB
•
32Mx16 resulting in 256 MB
•
64Mx16 resulting in 512 MB
•
128Mx16 resulting in 1GB
For UMA-32 bit mode, memory controller supports these two-chip configurations
•
16Mx16 resulting in 64 MB
•
32Mx16 resulting in 128 MB
•
64Mx16 resulting in 256 MB
•
128Mx16 resulting in 512MB
For UMA-16 bit, memory controller supports these single-chip configurations
•
16Mx16 resulting in 32 MB
•
32Mx16 resulting in 64 MB
•
64Mx16 resulting in 128 MB
•
128Mx16 resulting in 256 MB
For non-UMA 32/16-bit and non-UMA 16/16-bit modes, memory controller supports these three-chip and two-chip
configurations. The 16-bit memory controller is dedicated for the AVC decoder and used for the pixel operation of the
decoder code core. The 16-bit DDR2 interface supports the following configurations
•
16Mx16 resulting in 32 MB
•
32Mx16 resulting in 64 MB
By using 32/16 non-UMA mode, the BCM7405 can support 64+32 MB (96 MB), when 64 MB is connected to the 32-bit
interface and 32 MB is connected to 16-bit interface. The 128+64 MB (192 MB) device configuration can also be supported
by the BCM7405 when 128 MB is hooked up to the 32-bit interface and 64 MB is connected to the 16-bit interface.
The 16-bit DDR memory controller core (for non-UMA modes) is not directly accessible by the main processor (mem-mem
DMA only) so it can not be used for other applications.
