2/24/2008 9T6WP
Preliminary Hardware Data Module
BCM7405
06/29/07
Timing and AC Characteristics
Bro a d c o m Co rp o r a ti o n
Document
7405-1HDM00-R
EBI Timing Page 1-159
EBI T
IMING
A
SYNCHRONOUS
R
EAD
T
RANSFER
Figure 1-44: Async Read Timing Diagram
Table 1-30: Async Read Timing Parameters
Description
Symbol
Min
Max
Units
Delay time: EBI_CLK rising to EBI_ADDR[25:0] or EBI_TSIZE[1:0] valid
t
1
3
13.5
ns
Delay time: EBI_CLK rising to EBI_CSb[n] low or high (CSHold=0)
t
2
3
13.5
ns
Delay time: EBI_CLK falling to EBI_CSb[n] low or high(CSHold=1)
t
3
3
13.5
ns
Delay time: EBI_CLK rising to EBI_RDb or EBI_DSb low or high
t
4
3
13.5
ns
Setup time: EBI_DATA[15:0] valid to EBI_CLK rising
t
10
7
–
ns
Hold time: EBI_DATA[15:0] valid after EBI_CLK rising
t
11
0
–
ns
Note:
Load is 35 pF for all EBI pins.
Data
Data
t
1
t
2
t
3
t
4
t
4
t
10
EBI_CLK
EBI_ADDR[25:0]
EBI_TSIZE[1:0]
EBI_CSb[n]
EBI_RDb, EBI_DSb
EBI_DATA[15:0]
t
11
t
3
t
1
