2/24/2008 9T6WP
BCM7405
Preliminary Hardware Data Module
Functional Description
06/29/07
Bro a d c o m C o rp o r a ti o n
Page 1-94
Power Features
Document
7405-1HDM00-R
2
The DDR sequencer detects an idle state for a programmed period, and starts the Power Save mode.
3
The sequencer sends a self-refresh command to DDR device followed by pulling CKE low, and stops the clock to DDR
device by disabling enable signal to clock pads. All the internal blocks of the BCM7405 memory controller continue to be
clocked.
4
As soon as a request to DRAM access is made, the sequencer starts the self-refresh exit process by enabling the clock
and CKE and sending auto-refresh commands to DDR device. This takes up to 225 DDR clocks (200 clocks for self-
refresh exit, others issue auto refresh, and so on).
P
OWER
-U
P
S
EQUENCE
The BCM7405 can accept any of the power rail sequence but all should be stable within 20 ms from any power rail raising
past 50 mV. The RESETb signal should be held active for 75 ms after the last power rail has stabilized.
depicts the valid power-up sequence.
Figure 1-34: Power-Up Sequence Waveforms Without On-chip Voltage Regulator
50 mV
First voltage (either 1.2V, 1.8V,
2.6V, or 3.3V) reaching 50 mV
Last Voltage (either 1.2V, 1.8V, 2.6V or
3.3V) to reach minimum operating
voltage.
RESET# Input
All Power rails above
minimum operating voltage.
1.2V rail at 1.14V or
1.8V rail at 1.71V or
2.6V rail at 2.47V or
3.3V rail at 3.135V
20 ms
75 ms
min.
Thold > 0
All four voltages (1.2V, 1.8V, 2.6V, and 3.3V) should ramp up within 20 ms total, in any order (there is
no sequence required). The RESET# input into the Broadcom chip should be held in reset (low) while
the votages ramp up and for at least an additional 75 milliseconds after the last voltage comes up to it’s
minimum operating voltage.
