Broadcom BCM7405, General Information Manual

Page: 168 / 194

2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Timing and AC Characteristics
06/29/07
Bro a d c o m C o rp o r a ti o n
Page 1-154 I2S Audio/Compressed I2S Output Timing Document 7405-1HDM00-R
I
2
S A
UDIO
/C
OMPRESSED
I
2
S O
UTPUT
T
IMING
Figure 1-39: I
2
S Audio/Compressed I
2
S Output Timing Diagram
Table 1-25: I
2
S Audio/Compressed I
2
S Output Timing Parameters
Description Symbol Min Typical Max Units
edge of sclk to changing lr clock clk_lr –4 – 4 ns
edge of sclk to changing data clk_d –4 – 4 ns
sclk duty cycle sclk_dc – 50 – %
sclk period for Fs = 96 kHz T_96kHz – 163 – ns
sclk frequency for Fs = 96 kHz F_96kHz – 6.144 – MHz
sclk period for Fs = 48 kHz T_48kHz – 326 – ns
sclk frequency for Fs = 48 kHz F_48kHz – 3.072 – MHz
sclk period for Fs = 44.1 kHz T_44kHz – 354 – ns
sclk frequency for Fs = 44.1 kHz F_44kHz – 2.8224 – MHz
sclk period for Fs = 32 kHz T_32kHz – 488 – ns
sclk frequency for Fs = 32 kHz F_32kHz – 2.048 – MHz