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Request function and the IEEE 488.2 Status Reporting structure.
4.11.1 The Status Byte
Status summary information is communicated from the device to the controller using the Status Byte (STB). The
STB is composed of single-bit summary-messages, each summary message summarizing an overlying Status Data
Structure. By examining the content of the STB, the controller gains some information concerning the instrument's
status.
The STB bits are defined as follows:
Bit 0: Unused
Bit 1: Unused
Bit 2: Error/event queue summary message (EVQ). This bit is set if the queue is not empty.
Bit 3: Questionable Status summary message.
Bit 4: Message Available (MAV) summary message. This bit is set whenever all or part of a message is available for
the controller to read. The controller may be ready to read the response message before it is available, in
which case it can either wait until this bit is set, or it can start to read. In the second case, the controller
timeout must be set so that the read action will not be aborted before the message has been read.
Bit 5: Event Status Bit (ESB) summary message. This bit is set to indicate that one or more of the enabled standard
events have occurred.
Bit 6: Request Service (RQS). This bit is set when the device is actively requesting service.
Bit 7: Operation Status summary message. No Operation Status events are defined in the instrument, and so this bit
is never set.
The STB is read by the controller during a serial poll. If the RQS bit was set, it is then cleared. The STB may
also be read by the *STB? common query.
4.11.2 Service Request Enabling
Service request enabling allows the user to select which Status Byte summary messages may cause the device to
actively request service. This is achieved using the Service Request Enable Register, which is an 8-bit register
whose bits correspond to those of the STB. The RQS bit in the STB is set when a bit in the STB is set, and its
corresponding bit in the service request enable register is set.
The service request enable register is set using the *SRE common command, and read using the *SRE? common
query.
4.11.3 Standard Event Status Register
The Standard Event Status Register (SESR) is defined by IEEE 488.2. It is implemented in the instrument as a
byte, whose bits have the following definitions:
Bit 0: Operation Complete (OPC). This bit is set in response to the *OPC common command being executed.
Bit 1:
Request Control (RQC). Not implemented.
Bit 2:
Query Error (QYE). This bit is set when either the controller is attempting to read data from the device when
none is available, or when data prepared for the controller to read has been lost.
Bit 3:
Device-Specific Error (DDE). This bit is set to indicate that a device operation did not execute due to some
device condition. For example, trying to recall an uninitialized device stored setting.
Bit 4:
Execution Error (EXE). This bit is set when the device could not execute a command, due to the command
being outside of its capabilities. For example, a parameter being out of range.
Bit 5:
Command Error (CME). This bit is set to indicate an error in the command syntax.
