Anritsu MS8608A, Operation Manual, Page: 241 / 338

SECTION 4 STATUS STRUCTURE
4-9
Standard Event Status Register
Bit definition of Standard Event Status Register
The diagram below shows the operation of the Standard Event Status Register.
disabled = 0, enabled = 128(2
7
)
disabled = 0, enabled = 64 (2 6 )
disabled = 0, enabled = 32 (2 5 )
disabled = 0, enabled = 16 (2
4
)
disabled = 0, enabled = 8 (2 3 )
disabled = 0, enabled = 4 (2
2
)
disabled = 0, enabled = 2 (2 1 )
disabled = 0, enabled = 1 (2 0 )
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
&
Logical OR
Standard Event Status
Enable Register
Set by *ESE n
Read by *ESE?
Read by*ESR?
Power on (PON)
User request (URQ)...Not used
Command error (CME)
Execution (EXE)
Device-dependent (DDE)
Query error (QYE)
Request for bus cotrol right (RQC)...Not used
Operation complete (OPC)
Standard Event Status Register
EBS summary message bit
(to Status Byte register bit 5)
The Standard Event Status Enable (ESE) Register on the left is used to select which bits
in the corresponding Event Register will cause a TRUE summary message when set.
Bit Event name Description
7 Power on (PON-Power on)
A transition from power-off to power-on occurred during
the power-up procedure.
6
Not used
5
Command error
(CME-Command Error) An illegal program message or a misspelled command was
received.
4
Execution error
(EXE-Execution Error)
A legal but unexecutable program message was received.
3
Device-dependent error
(DDE-Device-dependent Error) An error not caused by CME, EXE, or QYE occurred
(parameter error, etc.).
2
Query error
(QYE-Query Error)
An attempt was made to read data in the Output Queue
when it was empty. Or, the data in the Output Queue was
lost before it was read.
1
0
Operation complete
(OPC-Operation Complete) This bit becomes 1 when this instrument has processed
the
∗
OPC command.
Not used