Anritsu MS8608A, Operation Manual, Page: 236 / 338

SECTION 4 STATUS STRUCTURE
4-4
In the status model, IEEE488.1 status bytes are used for the lowest grade status. This
status byte is composed of seven summary message bits from the higher grade status
structure. To create these summary message bits, the status data structure is composed
of two types of register and queue models.
The register model consists of two registers used for recording events
and conditions encountered by a device. These two registers are the
Event Status Register and Event Status Enable Register. When the
results of the AND operation of both register contents are other than 0,
the corresponding bit of the status bit becomes 1. In other cases, the
corresponding bit becomes 0. When the result of their Logical OR is
1, the summary message bit also becomes 1. If the Logical OR result
is 0, the summary message bit also becomes 0.
The queue in the queue model
is used to sequentially record
the waiting status values or
information. If the queue is not
empty, the queue structure
summary message becomes 1.
If the queue is empty, the
message becomes 0.
Register model Queue model
In IEEE488.2, there are three standard models for the status data structure. Two are
register models and one is a queue model based on the register model and queue model
described above. The three standard models are:
1) Standard Event Status Register and Standard Event Status Enable Register
2) Status Byte Register and Service Request Enable Register
3) Output Queue
The Standard Event Status Register
has the same structure as the
previously described register model.
In this register, the bits for eight types
of standard events encountered by a
device are set as follows:
1)
Power on
2)
User request
3)
Command error
4)
Execution error
5)
Device-dependent error
6)
Query error
7)
Request for bus control right
8)
Operation complete
The Logical OR output bit is
represented by Status Byte Register bit
5 (DIO6) as a summary message for
the Event Status Bit (ESB).
The Status Byte Register is a
register in which the RQS bit and
the seven summary message bits
from the status data structure can
be set. This register is used
together with the Service Request
Enable Register. When the results
of the OR operation of both
register contents are other than 0,
SRQ becomes ON. To indicate
this, bit 6 of the Status Byte
Register (DIO7) is reserved by the
system as the RQS bit. The RQS
bit is used to indicate that there is a
service request for the external
controller. The mechanism of
SRQ conforms to the IEEE488.1
standard.
The Output Queue has
the structure of the
queue model described
above. Status Byte
Register bit 4 (DIO5) is
set as a summary
message for Message
Available (MAV) to
indicate that there is
data in the output buffer.
Standard Event Status Register Status Byte Register Output Queue