UG-707
ADV8005 Hardware Reference Manual
7.4.1.
Output Oversampling
encoder core includes two on-chip phase-locked loops (PLLs) that allow for oversampling of SD, ED, and HD video data.
Oversampling effectively increases the bandwidth of the output video data, which means that expensive analog filters are not needed at the DAC
outputs, thus resulting in reduced BOM costs.
shows the various oversampling rates supported in the
encoder core.
Two PLLs are used for oversampling the analog output video, depending on the mode. When SD modes only are being output, PLL1 is used for
output oversampling. When HD modes only are being output, PLL2 is used for output oversampling. In dual modes where both SD and HD
formats are being output, PLL1 and PLL2 are both used for SD and HD video respectively.
pll_pdn
, Encoder Map,
Address 0xE400[1]
This bit is used to control the PLL and oversampling. This control allows the internal PLL 1 circuit to be powered down and the
oversampling feature to be switched off. By default this is disabled, setting this bit to 0 enables this feature.
Function
pll_pdn
Description
0
PLL On
1 (default)
PLL Off
Table 71: Output Oversampling Modes and Rates
Input Mode
Register 0xE401, Bits[6:4]
PLL and Oversampling Control
Register 0xE400, Bit 1
Oversampling Mode and Rate
SD only
1
SD (2×)
SD only
0
SD (16×)
ED only
1
ED (1×)
ED only
0
ED (8×)
HD only
1
HD (1×)
HD only
0
HD (4×)
SD and ED
1
SD (2×) and ED (8×)
SD and ED
0
SD (16×) and ED (8×)
SD and HD
1
SD (2×) and HD (4×)
SD and HD
0
SD (16×) and HD (4×)
ED only (at 54 MHz)
1
ED only (at 54 MHz) (1×)
ED only (at 54 MHz)
0
ED only (at 54 MHz) (8×)
7.4.2.
Subcarrier Frequency Lock (SFL) Mode
encoder core can be used in Subcarrier Frequency Lock (SFL) mode (
rtcen
= 11). When SFL mode is enabled, the SFL pin can
receive a serial digital stream from an ADI decoder (for example, ADV784x) which is used to lock the subcarrier frequency. This enables the
encoder to stay locked to a video pixel clock which drifts over the time (this happens with poor video sources like VCRs). Since the
color subcarrier in SD modes is generated from the input pixel clock to the
, these variations on its frequency may alter the final color
on the CBVS or Y/C output.
Hence, the SFL mode allows the
encoder core to automatically alter the subcarrier frequency to compensate for these line length
variations. When the part is connected to a device such as an ADV784x video decoder that outputs a digital data stream in the SFL format, the
part automatically changes to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67-bits wide, and the
subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock cycles long.
rtcen[1:0]
, Encoder Map,
Address 0xE484[2:1]
This signal is used to select the Sub-carrier Frequency Lock mode. The value of these register bits along with the status of the SFL pin
determine the operation.
Function
rtcen[1:0]
Description
00 (default)
Disabled.
11
SFL mode enabled.
Rev. A | Page 248 of 317
