Analog Devices ADV8005, Hardware Reference Manual

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UG-707 ADV8005 Hardware Reference Manual
InfoFrame
Map Address R/W Register Name Byte Name
0xE361 R vs_inf_pb_0_14 Data Byte 13
0xE362 R vs_inf_pb_0_15 Data Byte 14
0xE363 R vs_inf_pb_0_16 Data Byte 15
0xE364 R vs_inf_pb_0_17 Data Byte 16
0xE365 R vs_inf_pb_0_18 Data Byte 17
0xE366 R vs_inf_pb_0_19 Data Byte 18
0xE367 R vs_inf_pb_0_20 Data Byte 19
0xE368 R vs_inf_pb_0_21 Data Byte 20
0xE369 R vs_inf_pb_0_22 Data Byte 21
0xE36A R vs_inf_pb_0_23 Data Byte 22
0xE36B R vs_inf_pb_0_24 Data Byte 23
0xE36C R vs_inf_pb_0_25 Data Byte 24
0xE36D R vs_inf_pb_0_26 Data Byte 25
0xE36E R vs_inf_pb_0_27 Data Byte 26
0xE36F R vs_inf_pb_0_28 Data Byte 27
The Vendor Specific InfoFrame registers are considered valid if the following two conditions are met:
•
vs_infoframe_det is 1.
•
vs_inf_cksum_err is 0. This condition applies only if always_store_inf is set to 1.
5.10. PACKET REGISTERS
5.10.1. ISRC Packet Registers
Table 39 and Table 40 provide lists of the readback registers available for the ISRC packets. Refer to the HDMI 1.4 specifications for a detailed
explanation of the ISRC packet fields.
Table 39: ISRC1 Packet Registers
InfoFrame
Map Address R/W Register Name Packet Byte No. 1
0xF2 R/W isrc1_packet_id[7:0] Packet Type Value
0xF3 R isrc1_header1 HB1
0xF4 R isrc1_header2 HB2
0x8C R isrc1_pb_0_1 PB0
0x8D R isrc1_pb_0_2 PB1
0x8E R isrc1_pb_0_3 PB2
0x8F R isrc1_pb_0_4 PB3
0x90 R isrc1_pb_0_5 PB4
0x91 R isrc1_pb_0_6 PB5
0x92 R isrc1_pb_0_7 PB6
0x93 R isrc1_pb_0_8 PB7
0x94 R isrc1_pb_0_9 PB8
0x95 R isrc1_pb_0_10 PB9
0x96 R isrc1_pb_0_11 PB10
0x97 R isrc1_pb_0_12 PB11
0x98 R isrc1_pb_0_13 PB12
0x99 R isrc1_pb_0_14 PB13
0x9A R isrc1_pb_0_15 PB14
0x9B R isrc1_pb_0_16 PB15
0x9C R isrc1_pb_0_17 PB16
0x9D R isrc1_pb_0_18 PB17
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