ADV8005 Hardware Reference Manual
UG-707
The CPOL/CPHA can be configured through the following I
2
C registers.
spi_master_cpol
, IO Map,
Address 0x1A14[1]
This bit is used to select the SPI master clock polarity.
Function
spi_master_cpol
Description
0 (default)
Idle state, clock is low
1
Idle state, clock is high
spi_master_cpha
, IO Map,
Address 0x1A14[0]
This bit is used to select the SPI master clock phase.
Function
spi_master_cpha
Description
0 (default)
Negedge used
1
Posedge used
4.2.9.
OSD Initialization
To configure
to use the OSD, the following I
2
C writes are required:
0x1A14=0x0C: SPI mode select
0x1ACE=0x00: SPI bus enable
0x1ACC=0x10: Configure OSD HW int
Further SPI writes are required but these are controlled through the OSD.
Rev. A | Page 181 of 317
