UG-707
ADV8005 Hardware Reference Manual
ccap_odd_en
, IO Map,
Address 0x1A4C[3]
This bit is used to enable/disable closed caption data extraction on the odd field.
Function
ccap_odd_en
Description
0 (default)
Disable closed caption data extraction on odd field
1
Enable closed caption data extraction on odd field
ccap_even_en
, IO Map,
Address 0x1A4C[2]
This bit is used to enable/disable closed caption data extraction on the even field.
Function
ccap_even_en
Description
0 (default)
Disable closed caption data extraction on even field
1
Enable closed caption data extraction on even field
cgms_anc_en
, IO Map,
Address 0x1A4C[1]
This bit is used to enable/disable CGMS data extraction on the even field.
Function
cgms_anc_en
Description
0 (default)
Disable CGMS data extraction on even field
1
Enable CGMS data extraction on even field
wss_anc_en
, IO Map,
Address 0x1A4C[0]
This bit is used to enable/disable WSS data extraction on the even field.
Function
wss_anc_en
Description
0 (default)
Disable WSS data extraction on even field
1
Enable WSS data extraction on even field
anc_delay[1:0]
, IO Map,
Address 0x1A4D[1:0]
This bit is used to set the delay on ancillary data in vsyncs. The interlaced input delay will be in fields and the progressive delay will be in
frames. Decoded data is firstly transferred onto input vsync and then output vsync, this will be the base delay with a setting of 0. Every
increment above this adds one input vsync delay.
did_a[7:0]
, IO Map,
Address 0x1A4A[7:0]
This register is used to specify the value of the DID sent in the ancillary stream with VBI decoded data.
sdid_a[7:0]
, IO Map,
Address 0x1A4B[7:0]
This register is used to specify the value of the SDID sent in the ancillary stream with VBI decoded data.
2.2.9.
Resets
This section documents the register bits used for resetting various sections of the
. These resets can be used by the system controller
to reset individual sections of the device without having to reset the whole part. If the whole device needs to be reset, this can be implemented
by setting the global reset,
. All these register bits are self clearing, which means that when set to 1, they are set back to 0 after the
appropriate section has been reset.
Refer to Section
for more information on the reset strategy for the HDMI Tx.
svsp_reset
, IO Map,
Address 0x1AFD[7] (Self-Clearing)
This bit is used to reset the Secondary VSP.
Function
svsp_reset
Description
0 (default)
Default
1
Reset
Rev. A | Page 76 of 317
