UG-707
ADV8005 Hardware Reference Manual
enc_reset
, IO Map,
Address 0x1AFE[6] (Self-Clearing)
This bit is used to reset the HD and SD encoders.
Function
enc_reset
Description
0 (default)
Default
1
Reset
tx2_reset
, IO Map,
Address 0x1AFE[5] (Self-Clearing)
This bit is used to reset the HDMI TX2.
Function
tx2_reset
Description
0 (default)
Default
1
Reset
tx1_reset
, IO Map,
Address 0x1AFE[4] (Self-Clearing)
This bit is used to reset the HDMI TX1.
Function
tx1_reset
Description
0 (default)
Default
1
Reset
dpll_reset
, IO Map,
Address 0x1AFE[2] (Self-Clearing)
This bit is used to reset the DPLL clock generator.
Function
dpll_reset
Description
0 (default)
Default
1
Reset
xtal_reset
, IO Map,
Address 0x1AFE[0] (Self-Clearing)
This bit is used to reset all the clocks in the device and peripheral logic in the core including the interrupt generator and the automatic clock
selection.
Function
xtal_reset
Description
0 (default)
Default
1
Reset
main_reset
, IO Map,
Address 0x1BFF[7] (Self-Clearing)
This bit is used to initiate a global reset for the device.
Function
main_reset
Description
0 (default)
Default
1
Reset
2.2.10.
Image Processing Colorimetry Breakdown
The
performs its image processing in the YUV format except for the internal OSD which is generated in RGB. The internally generated
OSD is muxed with the external OSD (which can be in either YUV or RGB) before being input into a CSC. The CSC converts all input signals
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