Analog Devices ADV8005, Hardware Reference Manual

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ADV8005 Hardware Reference Manual UG-707
pvsp_vid_clk_update , IO Map, Address 0x1A3A[4]
This bit is used to trigger the open loop period to be captured in the DPLL. A low to high transition triggers the action.
Function
pvsp_vid_clk_update Description
0 (default) Do not update open_loop_period in DPLL
1 Update open_loop_period in DPLL
For example, the following procedure updates the PVSP DPLL clock period:
1A 1A39 0A – Put the DPLL into
ADV8005 (scaler) mode
1A 1A3B XX – Configure DPLL clock period setting
1A 1A3C XX – Configure DPLL clock period setting
1A 1A3D XX – Configure DPLL clock period setting
1A 1A3E XX – Configure DPLL clock period setting
1A 1A3A 80 – Recommended setting
1A 1A3A 90 – Recommended setting
Once configured, the clock in
Figure 37 is programmed for operation.
2.2.4.2. SVSP Output Timing
The following registers are programmed for the SVSP.
svsp_vid_clk_period[33:0] , IO Map, Address 0x1A3F[1:0]; Address 0x1A40[7:0]; Address 0x1A41[7:0]; Address 0x1A42[7:0]; Address
0x1A43[7:0]
This signal is used to set the open_loop_period of the DPLL section. This should be programmed based on the value calculated from the
given equations.
svsp_vid_clk_update , IO Map, Address 0x1A3F[4]
This bit is used to trigger the open loop period to be captured in the DPLL. A low to high transition triggers the action.
Function
svsp_vid_clk_update Description
0 (default) Do not update open_loop_period in DPLL
1 Update open_loop_period in DPLL
For example, the following procedure for updating the SVSP DPLL clock period is very similar to that of the PVSP:
1A 1A39 0A – Put the DPLL into
ADV8005 mode
1A 1A40 XX – Configure DPLL clock period setting
1A 1A41 XX – Configure DPLL clock period setting
1A 1A42 XX – Configure DPLL clock period setting
1A 1A43 XX – Configure DPLL clock period setting
1A 1A3F 80 – Recommended setting
1A 1A3F 90 – Recommended setting
Once configured, the clock in
Figure 37 is programmed for operation.
2.2.4.3. Frame Tracking
The ADV8005 employs frame tracking on its scaler outputs. There will always be some error in the input frame rate versus the ideal frame rate.
This could cause frame drops or repeats at the output. Frame tracking allows the output timing to track the input timing in such a way that
eliminates frame drops and repeats while also remaining immune to discontinuities in the input. The system can be fully frequency and phase
locked using . If phase locked is selected, there will be an integer frame latency from input to output. If frequency locked is selected, there could
be a non integer frame latency number from input to the output. Selecting phase error latency is the recommended setting.
Frame tracking results in an integer ratio relationship between the input and output frame rates of 1:1, 2:1, 1:2, 5:2 or 2:5. For example, if scaling
Rev. A | Page 67 of 317