ADV8005 Hardware Reference Manual
UG-707
exosd_in_id[7:0]
, IO Map,
Address 0x1B6C[7:0]
This register is used to specify the video_id relative to CEA 861.
Function
exosd_in_id[7:0]
Description
0x01
CEA 861 VIC 1 (480p_60 640)
0x02
CEA 861 VIC 2 (480p_60)
0x03
CEA 861 VIC 3 (480p_60)
0x04
CEA 861 VIC 4 (720p_60)
0x05
CEA 861 VIC 5 (1080i_60)
0x06
CEA 861 VIC 6 (480i_60)
0x07
CEA 861 VIC 7 (480i_60)
0x08
CEA 861 VIC 8 (240p_60)
0x09
CEA 861 VIC 9 (240p_60)
0x10
CEA 861 VIC 16 (1080p_60)
0x11
CEA 861 VIC 17 (576p_50)
0x12
CEA 861 VIC 18 (576p_50)
0x13
CEA 861 VIC 19 (720p_50)
0x14
CEA 861 VIC 20 (1080i_50)
0x15
CEA 861 VIC 21 (576i_50)
0x16
CEA 861 VIC 22 (576i_50)
0x17
CEA 861 VIC 23 (288p_50)
0x18
CEA 861 VIC 24 (288p_50)
0x1F
CEA 861 VIC 31 (1080p_50)
0xFC
CEA 861 VIC 252 (288p_50)
0xFD
CEA 861 VIC 253 (240p_60)
0xFE (default)
CEA 861 VIC 254 (480i_60)
0xFF
CEA 861 VIC 255 (576i_50)
rx_in_id[7:0]
, IO Map,
Address 0x1B96[7:0]
This register is used to specify the VIC relative to CEA 861.
Function
rx_in_id[7:0]
Description
0x06
CEA861 VIC 6 (480i60 2x)
0x07
CEA861 VIC 7 (480i60 2x)
0x08
CEA861 VIC 8 (240p60 2x)
0x09
CEA861 VIC 9 (240p60 2x)
0x15
CEA861 VIC 21 (576i50 2x)
0x16
CEA861 VIC 22 (576i50 2x)
0x17
CEA861 VIC 23 (288p50 2x)
0x18
CEA861 VIC 24 (288p50 2x)
The
can output a large number of video formats including many common graphics resolutions. To enable the PVSP and SVSP cores
to output these frequencies, the output timing clocks must first be programmed. The output clocks for both the PVSP and SVSP are shown in
Figure 37: PVSP/SVSP Output Clock Configure
For the PVSP and SVSP, the correct clocks must be configured manually. This can be done using the DPLL period registers, which allows the
user to program the sampling rate for the appropriate output format by I
2
C. The equation for calculating this I
2
C value is provided in
Primary
VSP
Secondary
VSP
Primary VSP
dpll clock
Secondary VSP
dpll clock
Primary
VSP
Secondary
VSP
Primary VSP
dpll clock
Secondary VSP
dpll clock
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