Analog Devices ADV8005, Hardware Reference Manual

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UG-707 ADV8005 Hardware Reference Manual
MHz
period phase dpll
27 12 64
1
_ _
× ×
≡
Equation 1: Calculating DPLL Phase Period
Once the dpll_phase_period is calculated,
Equation 2 is used to calculate the dpll_clock_period.
period phase dpll
period clock output
period clock dpll
_ _
2 _ _
_ _
22
×
≡
Equation 2: Calculating DPLL Clock Period
where output_clock_period is the period of the desired output sampling frequency.
For example, for HD video, the output clock sampling frequency would be 148.5 MHz. This equation returns a decimal value. Once calculated,
this should be converted to hex and written to
pvsp_vid_clk_period[33:0] and svsp_vid_clk_period[33:0] . Table 4 outlines some common
resolutions and their associated dpll_clock_period values.
Table 4: Example Values for dpll_clock_period
Active Resolution Frame Rate (Hz) Sampling
Frequency (MHz)
dpll_clock_period
(Hex)
720 x 480i 29.97 13.5 0x180000000
720 x 480p 59.94 27 0x0C0000000
720 x 576i 25 13.5 0x180000000
720 x 576p 50 27 0x0C0000000
960 x 480i 29.97 18 0x120000000
960 x 576i 25 18 0x120000000
1280 x 720p 59.94 74.175 0x045E386DC
1280 x 720p 60 74.25 0x045D1745D
1920 x 1080i 29.97 74.175 0x045E386DC
1920 x 1080i 30 74.25 0x045D1745D
1920 x 1080p 59.94 148.35 0x022F1C36E
1920 x 1080p 60 148.5 0x022E8BA2F
1920 x 1080i 25 74.25 0x045D1745D
1920 x 1080p 50 148.5 0x022E8BA2F
Depending on the sampling frequency required, the following registers need to be programmed with this DPLL clock period.
Note: To enable the DPLL to configure the correct clocks for the ADV8005 , register 0x0039 must be set to 0x0A. This register must always be
configured before the following registers are set. This configures the ADV8005 clock generators to generate the clocks for the ADV8005 .
2.2.4.1. PVSP Output Timing
The following registers are programmed for the PVSP.
pvsp_vid_clk_period[33:0] , IO Map, Address 0x1A3A[1:0]; Address 0x1A3B[7:0]; Address 0x1A3C[7:0]; Address 0x1A3D[7:0]; Address
0x1A3E[7:0]
This register is used to set the open_loop_period of the DPLL section. This should be programmed based on the value calculated from the
given equations.
Rev. A | Page 66 of 317