ADV8005 Hardware Reference Manual
UG-707
Figure 36: Configuring Input Port Clock
Serial
Video
RX
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
RxC+
RxC-
Y
Cb
Cr
HS
VS
CK
Set by rx_in_id
Y
Cb
Cr
HS
VS
CK
P[35]
P[0]
VS
HS
DE
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
RxC+
RxC-
Y
Cb
Cr
HS
VS
CK
Y
Cb
Cr
HS
VS
CK
P[35]
P[0]
VS
HS
DE
Y
Cb
Cr
HS
VS
CK
OSD_IN[35]
OSD_IN[0]
OSD_VS
OSD_HS
OSD_DE
Y
Cb
Cr
HS
VS
CK
Main
TTL
Inputs
Secondary
TTL
Inputs
Set by vid_in_id
Set by exosd_in_id
Rev. A | Page 63 of 317
