ADV8005 Hardware Reference Manual
UG-707
Rev. A | Page 165 of 317
svsp_track_offset[20:0]
, IO Map,
Address 0x1A97[4:0]; Address 0x1A98[7:0]; Address 0x1A99[7:0]
This signal is used to program the delay on the output timing of vsyncs from the Secondary VSP.
Function
svsp_track_offset[20:0] Description
0 (default)
input and output vsync coincident
1
1 xltal clk between input nad output vsync
3.7.
PROGRESSIVE TO INTERLACED CONVERSION
has two progressive to interlaced converters (P2I).
The primary P2I converter is an independent block to which the PVSP, OSD and inputs can be connected. The primary P2I converter can
convert from any progressive format to its interlaced equivalent. The input to the primary P2I converter is selected by
The secondary P2I converter is connected directly to the SVSP. The secondary P2I converter cannot convert from 1080p to 1080i but can handle
all other progressive to interlaced conversions.
p2i_inp_sel[3:0]
, IO Map,
Address 0x1A06[7:4]
This signal is used to select the video source for the Progressive to Interlaced converter.
Function
p2i_inp_sel[3:0] Description
0x00
From Primary VSP
0x01
From Internal OSD Blend 1
0x02
From EXOSD TTL Input
0x03
From RX Input
0x04
From Video TTL Input
