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Analog Devices AD9361, Reference Manual

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AD9361 Reference Manual 

UG-570 

 | Page 9 of 128 

BASEBAND Rx ANALOG FILTER CALIBRATION 

The baseband Rx analog filter calibration tunes the cutoff 
frequency of the third-order Butterworth Rx anti-aliasing filter. 
The Rx filter is located just before the ADC in the Rx signal 
path and is normally calibrated to 1.4× the baseband channel 
bandwidth (BBBW). This calibration is important for Rx 
interferer rejection. Note that the BBBW is half the complex 
bandwidth and coerced between 28 MHz to 0.20 MHz for the 
equations used in this filter tuning. To calibrate this filter, the 
BBPLL is divided down using a divide by 1 to 511 divider 
dedicated to the Rx tuner block.  

𝐷𝑤𝑣𝑤𝑑𝑆𝑟  = 𝑆𝑆𝑤𝑆𝑤𝑛𝑔 �

𝐵𝐵𝑃𝐿𝐿

𝑀𝐻𝑧

 × 𝑙𝑛 (2)

𝐵𝐵𝐵𝑊

𝐷𝐸𝑆𝐼𝑅𝐸𝐷,𝑀𝐻𝑧

 × 2.8 × 𝜋

�

 

(

3

)

 

The Rx baseband analog filter calibration runs during the 
ad9361_set_rx_rf_bandwidth function. Calibration completion 
can be monitored on a control output pin or by reading the 
calibration control register until the Rx baseband filter 
calibration bit self clears.  
Because the filter calculation uses a ceiling function to generate 
the divider there will be some quantization of the corner 
frequency. If the quantization is too large it may be necessary to 
adjust the desired BBBW to compensate.  

𝐵𝐵𝐵𝑊

𝐴𝐶𝑇𝑈𝐴𝐿,𝑀𝐻𝑧

=

𝐵𝐵𝑃𝐿𝐿

𝑀𝐻𝑧

 × ln (2)

2.8 × π × 𝐷𝑖𝑣𝑖𝑑𝑒𝑟

(

4

)

 

𝐶𝑤𝑆𝑤𝑏𝑟𝑤𝑤𝑤𝑜𝑛 𝑇𝑤𝑚𝑆

𝑢𝑠

= 610 ×

ln (2)

𝐵𝐵𝐵𝑊

𝐴𝐶𝑇𝑈𝐴𝐿,𝑀𝐻𝑧

 × 2.8 × π

(

5

)

 

Table 5. Typical Rx Baseband Filter Calibration Times 

Standard 

Desired  

BBBW (MHz) 

BBPLL  

Frequency (MHz) 

RxBBF Divider (decimal) 

Actual BBBW (MHz) 

Maximum Calibration  

Time (µs) 

LTE 5 MHz 

2.5 

983.04 

31 

2.499 

19.236 

LTE 10MHz 

5 

983.04 

16 

4.841 

9.928 

LTE 15 MHz 

7.5 

737.28 

8 

7.262 

6.619 

LTE 20 MHz 

10 

983.04 

8 

9.683 

4.964 

Rev. A

Summary of Contents for AD9361

Page 1: ...e when using the evaluation board Additional information about the AD9361 registers can be found in the AD9361 Register Map Reference Manual While the register map is provided as a convince and informational for those who want to understand the low level operation of the part it is not recommended to attempt to create your own software Analog Devices provides complete drivers for the AD9361 for bo...

Page 2: ...ock 16 Main PLL Block 17 Charge Pump Current 18 RFPLL Loop Filter 18 VCO Configuration 18 VCO Calibration 18 VCO Vtune Measurement 18 Lock Detector 18 Synthesizer Look Up Table 19 TDD Mode Faster Lock Times 19 External LO 19 Baseband PLL BBPLL 19 BBPLL VCO 20 BBPLL Charge Pump 21 BBPLL Loop Filter 21 Fast Lock Profiles 22 Overview 22 Fast Lock Initial Wider BW Option 22 Configuring and Using a Fas...

Page 3: ...gnal Path Interface 69 Factory Calibrations 71 Overview 71 Internal DCXO 71 Tx RSSI Tx Monitor 71 Rx RSSI 71 Rx GM LNA Gain Step Calibration 72 Tx Power Out vs Tx Attenuation and Tx Power Out vs Carrier Frequency 72 Control Output 73 Overview 73 Description of Control Output Signals 74 0x035 0x00 Calibration Busy and Done 74 0x035 0x01 PLL Lock 75 0x035 0x02 Calibration Busy 75 0x035 0x03 Rx Gain ...

Page 4: ...onal Timing CMOS 101 Dual Port Full Duplex Mode CMOS 103 Dual Port FDD Functional Timing CMOS 104 Data Bus Idle and Turnaround Periods CMOS 105 Data Path Timing Parameters CMOS 105 LVDS Mode Data Path and Clock Signals 106 LVDS Mode Data Path Signals 107 LVDS Maximum Clock Rates and Signal Bandwidths 108 Dual Port Full Duplex Mode LVDS 109 Data Path Functional Timing LVDS 109 Data Path Timing Para...

Page 5: ...ow pass filter preceding the receive ADC and following the transmit DAC LUT Look up table several calibration and functions depend on either reading or storing look up tables for future use MGC Manual gain control where the BBP controls some or all of the gain control parameters in the AD9361 PLL Phase locked loop The AD9361 uses PLLs to generate the various clock rates within the chip as well as ...

Page 6: ...er VCO calibration Occurs automatically when integer frequency word written In TDD occurs when TXNRX changes logic level Rx 0x247 1 1 when locked Tx 0x287 1 1 when locked Baseband Rx analog filter tune Once update when BW changes 0x016 7 self clears when done Baseband Tx analog filter tune Once update when BW changes 0x016 6 self clears when done Baseband Tx secondary filter tune Once manual equat...

Page 7: ... will self clear If more than one calibration is enabled in a single register write the calibrations will progress in a set order controlled by a state machine in the AD9361 Table 2 shows the sequence of calibrations When the calibration sequence state holds a value of 0x1 the calibrations are complete Some calibrations depend on the results of previously run calibrations The Rx baseband filter an...

Page 8: ...he FDD state it may be a long time before a synthesizer VCO calibration occurs again In TDD the calibration time will need to be set to meet the TDD turnaround time while achieving the most accurate calibration possible In TDD the Rx VCO calibration will occur each time the receiver synthesizer is powered up when TxRNX switches from high to low logic level The Tx VCO calibration will occur each ti...

Page 9: ... 𝜋 3 The Rx baseband analog filter calibration runs during the ad9361_set_rx_rf_bandwidth function Calibration completion can be monitored on a control output pin or by reading the calibration control register until the Rx baseband filter calibration bit self clears Because the filter calculation uses a ceiling function to generate the divider there will be some quantization of the corner frequenc...

Page 10: ...analog filter calibration runs as part of the ad9361_set_tx_rf_bandwidth Calibration completion can be monitored on a control out pin or by reading calibration control until the Tx baseband filter calibration bit self clears 𝐵𝐵𝐵𝑊𝐴𝐶𝑇𝑈𝐴𝐿 𝑀𝐻𝑧 𝐵𝐵𝑃𝐿𝐿𝑀𝐻𝑧 ln 2 3 2 π 𝐷𝑖𝑣𝑖𝑑𝑒𝑟 7 𝐶𝑤𝑆𝑤𝑏𝑟𝑤𝑤𝑤𝑜𝑛 𝑇𝑤𝑚𝑆µ𝑠 355 ln 2 𝐵𝐵𝐵𝑊𝐴𝐶𝑇𝑈𝐴𝐿 𝑀𝐻𝑧 3 2 π 8 Similar to the baseband Rx analog filter there is quantization of the corner fr...

Page 11: ... OFFSET CALIBRATION It is recommended to run the baseband DC offset calibration once during device initialization in the ALERT state Since the baseband signal path does not change with different wireless standards or clock frequencies it should not need to be run again The baseband DC offset correction values are stored for all of the Rx analog baseband filter gain steps The correction words are a...

Page 12: ... chain By only running the calibration at gain indexes that actually change the front end gain the calibration time is reduced If the LUT does not hold a DC correction value for the current Rx gain index it will use the DC offset correction for the next higher gain index that was calibrated In the case of a split Rx gain table the calibration runs at each LMT gain index The RF DC offset tracking i...

Page 13: ...and to know when to refresh the Tx quadrature calibration The Tx quadrature calibration is a convergence algorithm but has a maximum calibration time described in the following paragraphs Equation 11 calculates the number of CLKRF clock cycles used for maximum calibration time CLKRF is the clock rate at the output of the Tx FIR filter after Tx FIR interpolation 94464 TxChannels TX s clockcycle CLK...

Page 14: ... making it more difficult for a baseband processor to correct the frequency error at startup and during operation This section describes the setup operation and recommended specification of the DCXO and reference clock DCXO SETUP AND OPERATION To use the DCXO connect an external crystal XO between the XTALP and XTALN pins of the AD9361 Valid crystal resonant frequencies range from 19 MHz to 50 MHz...

Page 15: ...tween DCXO and external reference clock is made in the ad9361_init function The level for the clock should be 1 3 V p p maximum lower swings can be used but will limit performance This signal can be a clipped sine wave or a CMOS signal The best performance will be seen with the highest slew rate possible The XTALN Pin M12 has an input resistance of 10 kΩ in parallel with 10 pF PHASE NOISE SPECIFIC...

Page 16: ...lo_freq function Each synthesizer must be configured and calibrated separately AD9361 PLL ARCHITECTURE The following sections show block diagrams of the AD9361 PLL that consist of the reference block the main PLL block and the LO GEN output block The VCO always operates between 6 GHz to 12 GHz REFERENCE BLOCK The reference frequency can be generated via the on chip DCXO or an external clock source...

Page 17: ...ly from 70 MHz to 6 GHz Figure 5 shows how the bands are created The synthesizer configuration registers loop filter integer and fractional words and VCO divider are calculated in the ad9361_rx_lo_freq and ad9361_tx_lo_freq function calls Figure 4 PLL Synthesizer Block Diagram Rx and Tx Synthesizers are Identical Figure 5 VCO Divider 8 9 PRE SCALER Σ Δ MODULATOR LC VCO PROGRAMMABLE INTEGRATED LOOP...

Page 18: ...izer has as much of the time as possible between frames to calibrate and lock Typical TDD calibration plus lock times are on the order of 45 µs to 60 µs For faster lock times refer to the TDD Mode Faster Lock Times section VCO CALIBRATION The time the calibration takes to complete is programmable Usually a fast calibration is appropriate for TDD systems and a slow calibration is appropriate for FD...

Page 19: ...Note that if the LO frequency is changed the VCOs will need to be recalibrated so it will retain the information pertaining to the new frequency EXTERNAL LO Unlike the internal synthesizers that always operate from 6 GHz to 12 GHz no matter the RF tune frequency the frequency applied when an External LO is used is 2 the desired RF LO frequency The range of the EXT LO signal is from 140 MHz to 8 GH...

Page 20: ...ference scaler block which is identical to but independent from the reference scaler blocks for the RFPLLs The reference block is configured to buffer multiply or divide the device reference frequency before passing to the to the BBPLL phase detector For best performance it is recommended that the BBPLL reference scaler block be configured such that the resulting BBPLL FREF is between 35 MHz to 70...

Page 21: ...s available This is an NMOS current source programmable from 0 µA to 316 µA BBPLL LOOP FILTER The loop filter is fully integrated on chip and is a standard passive Type II third order filter with five programmable components The filter is programmed by the ad9361_bbpll_set_rate function Figure 8 BBPLL Internal Loop Filter R2 and C3 Can Be Bypassed R1 C1 C2 R2 C3 VCO TUNE ICP 11668 009 Rev A ...

Page 22: ...ease the synthesizer s bandwidth for a programmable amount of time to further reduce lock time These values are defined in the profile information as well A profile can be recalled by either issuing a single SPI command that contains the desired profile number and transfer bit or alternatively a profile can be selected in hardware by setting the appropriate code on control input pins At that time ...

Page 23: ...ternal Addressing Program Address 7 4 Assignment Program Address 3 0 Assignment Written to 0x25D Location of Setup Words 0 profile0 0 Synthesizer Integer Word 7 0 0x231 D7 D0 1 profile1 1 Synthesizer Integer Word 10 8 0x232 D2 D0 2 profile2 2 Synthesizer Fractional Word 7 0 0x233 D7 D0 3 profile3 3 Synthesizer Fractional Word 15 8 0x234 D7 D0 4 profile4 4 Synthesizer Fractional Word 22 16 0x235 D6...

Page 24: ... C2 3 0 shift right by 4 0x27E D3 D0 0x27E D7 D4 B Not used B Loop Filter R1 3 0 Loop Filter R1 Init 3 0 0x27F D7 D4 Set per Init N calculation C Not used C VCO Varactor Reference Tcf 2 0 Rx VCO Divider 3 0 0x290 D6 D4 0x005 D7 D4 D Not used D VCO Cal Offset 3 0 shift left by 1 VCO Varactor Reference 3 0 0x278 D6 D3 0x291 D3 D0 E Not used E Force VCO Tune 7 0 0x277 D7 D0 F Not used F Force ALC wor...

Page 25: ...s the WAIT state with the AD9361 clocks disabled To enter the sleep state transition to the WAIT state then disable the AD9361 clocks in the BPLL register Figure 9 TDD and FDD State Diagrams for the Enable State Machine ENSM STATE DEFINITIONS The enable state machine contains the states shown in Table 13 Table 13 ENSM State Values ENSM State Name Value in ENSM State decimal Description SLEEP 0 WAI...

Page 26: ... 1 register Once in the ALERT state the AD9361 enables its RF synthesizers for the transmitters and receivers If for some reason the synthesizers did not calibrate correctly the ENSM will not be able to transition to the Rx or Tx states This feature protects the AD9361 from transmitting or receiving data when the synthesizers are not calibrated properly protecting the wireless spectrum Once in the...

Page 27: ... the Tx state if TXNRX is high In FDD the logic level of TXNRX is ignored The ENSM will exit the Rx Tx or FDD states when the ENABLE pin is pulled back to a logic low If the To Alert bit is clear the device will move from Rx Tx or FDD to the WAIT state To move from WAIT to ALERT in level mode the BBP can drive a pulse on the ENABLE pin or perform a SPI write to the Force Alert State bit If an ENAB...

Page 28: ...X high Rx signal chain enabled Tx signal chain enabled Operates like FDD state Note that since the ENSM always stays in the FDD state it never moves to the FDD FLUSH state Therefore the BBP must allow enough time after enabling the receive chain for the digital filters to flush and enough time after sending Tx data for the Tx to finish its transmission before disabling the corresponding signal cha...

Page 29: ...ynthesizer is disabled to save power While in the Tx state the Rx synthesizer is disabled In TDD the ENSM will generate a signal to recalibrate the correct VCO anytime the state of TXNRX changes This signal will be issued from the ENSM to the synthesizer after the delay in Rx or Tx Load Synth Delay has completed It is important to change the state of TXNRX as soon as the device moves into the ALER...

Page 30: ... Move to FDD state by setting Force Tx On bit in 0x014 5 WAIT Wait for FDD flush time six ADC_CLK 64 clock cycles SPIWrite 0x014 0x00 Move to Wait State by clearing 0x014 5 SPIWrite 0x009 0x00 Turn off all clocks sleep state 3 The AD9361 is now in the SLEEP state 4 To wake up the AD9361 enable digital clocks and BBPLL and then move into the ALERT state SPIWrite 0x009 0x17 Turn on all clocks assume...

Page 31: ...IR The first digital filter in the Tx signal path is a programmable polyphase FIR filter The Tx FIR filter can also interpolate by a factor of 1 2 or 4 or it can be bypassed if not needed This filter is controlled in the ad9361_set_tx_fir_config The filter taps are stored in 16 bit twos complement format and the number of taps is configurable between a minimum of 16 taps and a maximum of 128 taps ...

Page 32: ...t filter delays Each block s contribution to the total data latency is approximated using the following relationship S data f N t 1 2 12 where N is the filter order number of taps fS is the output sampling clock frequency after any interpolation Tx ANALOG FILTER BLOCKS Analog filtering after the DAC reduces spurious outputs by removing sampling artifacts and providing general low pass filtering pr...

Page 33: ... following the ADC in Figure 17 comprise the digital filtering for the receive path These programmable filters provide the bandwidth limiting and out of band noise and spurious signal reduction after digitization They also provide decimation needed to generate the correct data rates In each filter decimation is performed after the filtering has taken place ADC_CLK serves as the master clock refere...

Page 34: ...s can be used if the previously described clock ratio is satisfied This filter is setup using the ad9361_set_rx_fir_config function DIGITAL Rx BLOCK DELAY The digital Rx filter blocks are designed to minimize delay caused by mathematical operations so that the total delay is dominated by the inherent filter delays Each block s contribution to the total data latency is approximated using the follow...

Page 35: ... a gain control word to each of the variable gain blocks in Figure 19 A pointer to the table determines the control word values sent to each block as shown in Figure 19 Whether automatic gain control AGC or manual gain control MGC is used the pointer moves up and down the table which changes the gain in one or more of the blocks shown in Figure 18 The ADC maximum input 0 dBFS is 0 625 V peak Howev...

Page 36: ...the error between its samples and the input signal will cause the ADC to output more samples with values of 4 or 4 as it struggles to track the input signal Figure 20 shows how the ADC overload detector processes signals and how the thresholds are used Figure 20 ADC Over Range Detection Algorithm There are two programmable thresholds both of which are configured in the ad9361_set_rx_gain_control_m...

Page 37: ...re two different ways that the AD9361 can implement the gain table In full table mode there is one table for the receiver In split table mode the AD9361 splits the LMT and LPF tables apart and controls each independently with separate pointers If digital gain is enabled there is a third table that is independently controlled also with its own pointer Each receiver has its own set of two or three t...

Page 38: ...GITAL GAIN All modes MGC AGC and both gain table modes allow for the addition of digital gain The maximum allowable index for a full gain table is 90 d The maximum digital index is 31 d A standard full gain table with only analog gain has a maximum index of 76 d For the gain tables provided by Analog Devices this leaves 24 d indices left over for digital gain Alternative gain tables that reach the...

Page 39: ... LMT Gain bit 0x0FC D4 selects the gain change location For this option the gain table architecture still looks like Figure 22 If digital gain is enabled the BBP must change this gain by via SPI writes The CTRL_IN pins do not change digital gain in split table mode Alternatively if the Use AGC for LMT LPF Gain bit is set the AD9361 peak detectors determine where the gain changes With this option t...

Page 40: ... exceeds a threshold the gain does not necessarily change immediately In FDD systems there are typically brief periods such as those around slot boundaries that accommodate gain changes or other system parameter updates To accommodate this aspect of FDD protocols the AD9361 gain will only update after the gain update counter expires The counter is clocked at the ClkRF rate the input rate of the RF...

Page 41: ...ion Exceeded Counter and if it is exceeded the gain index is reduced SLOW ATTACK AGC AND GAIN TABLES In full table mode a single table controls the gain of all Rx signal path stages Table 18 shows the effect of peak overloads after their associated counters are exceeded Recall that a particular overload condition results in the gain index moving a program mable number of steps but the gain may cha...

Page 42: ...o an optimum gain Fast attack mode is configured with the ad9361_set_rx_gain_control_mode function When the AD9361 enters the Rx state the fast attack AGC state machine leaves State 0 and enters State 1 as shown in Figure 25 Its goal is to adjust the gain index such that an optimum receive gain is realized in a very short period of time The AGC progresses through several states on its way to Gain ...

Page 43: ... are stored for the fast attack AGC in full table mode The Case 1 step size is typically larger than Case 2 which itself is typically larger than Case 3 Table 21 shows the effects of various overloads when using a split table Figure 26 shows the split table architecture Note that the gain first decreases from the LMT table regardless of where the overload occurs When the gain index reaches the LMT...

Page 44: ...R AND PEAK OVERLOAD DETECT When the AGC enters State 3 it locks the gain This state can affect other portions of the AD9361 such as DC offset tracking updates and RSSI measurement start times The AGC continues to measure power and it keeps its large LMT large ADC and digital saturation overload detectors enabled If the Enable Gain Inc After Gain Lock bit is set and the Enable Incr Gain bit is set ...

Page 45: ... for the AGC to unlock the gain at the end of the burst Energy Lost Threshold or if the AD9361 exits the Rx State Unlocking the gain for an ADC overload is similar to a stronger signal test but is a peak detector rather than a power detector Unlocking the gain for a large LMT overload checks for large interfering signals and is a peak detector All of these tests are recommended for a typical fast ...

Page 46: ... how to use this feature If the thresholds are set correctly the typical setup which unlocks the gain when the AD9361 exits Rx mode or if the burst subframe ends is sufficient for most applications However if desired it is also possible to prevent the gain from unlocking in some instances see Table 26 The settings are dependent on whether the BBP will use the EN_AGC pin to unlock the gain If this ...

Page 47: ...ximate gain per the following tables all values for 2300 MHz Note that these are nominal values and some variation with carrier frequency temperature and process is expected for the LNA and mixer tables For accurate gain vs gain index values RF characterization needs to be done with the specific customer configuration Table 27 LNA Gain vs Index Internal LNA Index Internal LNA Gain dB 0 3 1 14 2 17...

Page 48: ...ain iLNA Gain in dB is next to iLNA index which is only used to add to other stages gains and which result in the estimated total receive path gain Again moving to the right results in the mixer index and next to that column is the mixer gain both of which are analogous to the iLNA index and iLNA gain described previously The 0x131 column to the right is the digital word that is a concatenation of...

Page 49: ...ttenuators that always provide a nominal amount of gain This gain is not controllable and the LNA cannot be bypassed In this case there are no programming changes necessary for the AD9361 Variable gain external LNAs use a control signal to select between two different gains Usually one is the high gain setting and the other is the low gain or bypass setting which is typically a loss The external L...

Page 50: ...51 Duration is always Rx sample rate cycles RSSI WEIGHTING If the Default RSSI Meas Mode bit is clear then the RSSI measurement duration consists of up to 4 values summed together Since each value can be different each value must be correctly weighted by its duration in Rx samples Weighting is calculated per Equation 20 If the Default RSSI Meas Mode bit is set the AD9361 automatically populates Mu...

Page 51: ...he receive path gain changes the RSSI word may differ from an expected value RSSI error typically is within 2 dB of the expected value which is satisfactory for most applications For greater RSSI accuracy the AD9361 uses a gain step calibration algorithm Running this calibration does not change the actual gain of the receive path but instead only affects RSSI LNA gain varies over frequency and the...

Page 52: ...00 Maximum LNA Gain 23 B8 Xx LNA Gain difference word for Index 0 22 2C Aa LNA Gain difference word for Index 1 8 10 Bb LNA Gain difference word for Index 2 3 6 Cc LNA Gain difference word for Index 3 0 0 Dd 4000 to 6000 Maximum LNA Gain 20 A0 Xx LNA Gain difference word for Index 0 18 24 Aa LNA Gain difference word for Index 1 8 10 Bb LNA Gain difference word for Index 2 3 6 Cc LNA Gain differenc...

Page 53: ...y and inject it into Rx1 7 Run the calibration by setting 0x016 D3 8 The calibration completes when 0x016 D3 clears 9 Read the LNA and Mixer error terms as shown in Table 38 into nonvolatile memory Table 38 Reading Gain Step Error Words from the AD9361 Line Number Command Addr Data Comment 1 SPIWrite 143 30 Setup to read LNA error words from Rx1 2 SPIWrite 140 00 Set LNA index address to 0 3 SPIRe...

Page 54: ...he field the words would be programmed into the internal tables for each receiver separately Table 40 Programming Gain Step Errors into the AD9361 in the Field Line Number Command Addr Data Comment 1 SPIWrite 143 61 Setup to write both Rx1 and Rx2 and start clock 2 SPIWrite 140 00 Set LNA index address to 0 3 SPIWrite 141 ff Write LNA index 0 error word from non volatile memory 4 SPIWrite 143 65 W...

Page 55: ...the entire table An attenuation word of zero results in 0 dB of attenuation The value of 359 d results in an overall attenuation of 89 75 dB The lookup table is hard coded in the AD9361 and it not programmable ATTENUATION WORD UPDATE OPTIONS The BBP can write attenuation words at any time using the ad9361_set_tx_attenuation function There are two choices for when the new attenuation word is implem...

Page 56: ...he AD9361 provides the ability to reuse the receiver circuitry by multiplexing the power detector into the receive path The receiver RSSI circuitry is then turned on during the transmit burst and results in accurate Tx RSSI measurements Refer to Figure 28 for a TPM circuit block diagram in a typical TDD system diagram Since the Tx signal is high level with respect to a Rx signal it is multiplexed ...

Page 57: ... R2 is to empirically tune it for desired TPM frequency response Use proper transmission line design techniques to design the signal path TL1 from the transmitter output coupler to the input of TPM The higher the frequency of operation the more critical this path becomes in terms of loss and signal reflections Figure 30 shows a measured TPM frequency response using the matching circuit and compone...

Page 58: ...eive low pass filter gain index in the 0 dB to 24 dB range TPM gain mode low or high is determined by a threshold in Tx Atten Threshold register Register 0x078 D7 D0 If the Tx Attenuation value Register 0x073 and Register 0x074 is equal to or less than the threshold the low gain index value is used and if the value is greater than the threshold the high gain index is used in the receive path Trans...

Page 59: ...evel ranges that correspond with these three different gain settings This approach uses the same Tx Mon Gain and GBBF gain settings across the whole attenuation range EXAMPLE OF TxMON CONFIGURATION AND MEASUREMENT OF TPM TRANSFER FUNCTION The following example is based on measured results using a direct connection from the Tx1 output to the Tx Mon input on an evaluation board The goal of the examp...

Page 60: ...e resulting linear dynamic range is 76 dB which is about 10 dB greater than the 66 dB dynamic range achievable with a single gain setting As Figure 33 shows the TPM TIA gain is not compensated by the Tx RSSI algorithm The 9 5 dB compensation that results in the solid line would occur in the baseband processor TPM TEST MODE It is possible to output TPM I Q data at the Rx data port in TDD mode in Tx...

Page 61: ...tilized in either a single ended mode or differential mode The transmitter output ports may only be utilized in a differential mode It is critical to have these interfaces working properly to achieve data sheet performance levels The main considerations are as follows Rx interface type single ended or differential Device to be interfaced such as filter balun T R switch external LNA external PA Sho...

Page 62: ...ferential interface configurations Note that matching networks will most likely be required to achieve optimum performance Given a single ended operation mode a positive side connection is delineated by the _P at the end of the Rx input port name and a negative side connection is delineated by the _N at the end of the Rx input port name The Rx differential input impedance varies over frequency and...

Page 63: ...IAL_L_OR_C_SE L_OR_C_STATUS FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2 32 2 57 2 82 3 07 3 32 3 57 3 82 4 07 4 32 4 57 4 82 5 07 5 32 5 57 5 82 6 00 Rx1A AND Rx2A SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx1A AND Rx2A SERIES EQUVALENT DIFFERENTIAL IMPEDANCE FREQUENCY 70MHz TO 6GHz 11668 039 250 0 50 100 150 200 ZDIFF MAGNITUDE FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 ...

Page 64: ..._C_SE L_OR_C_STATUS FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2 32 2 57 2 82 3 07 3 32 3 57 3 82 4 07 4 32 4 57 4 82 5 07 5 32 5 57 5 82 6 00 Rx1B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx1B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE FREQUENCY 70MHz TO 6GHz 11668 041 450 0 50 100 150 350 ZDIFF MAGNITUDE FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2 32 2 57 2 82 3 07 3...

Page 65: ...IAL_L_OR_C_SE L_OR_C_STATUS FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2 32 2 57 2 82 3 07 3 32 3 57 3 82 4 07 4 32 4 57 4 82 5 07 5 32 5 57 5 82 6 00 Rx1C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx1C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE FREQUENCY 70MHz TO 6GHz 11668 043 450 0 50 100 150 350 ZDIFF MAGNITUDE FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2 32 2 57 2 8...

Page 66: ...IAL_L_OR_C_SE L_OR_C_STATUS FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2 32 2 57 2 82 3 07 3 32 3 57 3 82 4 07 4 32 4 57 4 82 5 07 5 32 5 57 5 82 6 00 Rx2B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx2B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE FREQUENCY 70MHz TO 6GHz 11668 243 400 350 300 250 0 50 100 150 200 ZDIFF MAGNITUDE FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2...

Page 67: ...IAL_L_OR_C_SE L_OR_C_STATUS FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 07 2 32 2 57 2 82 3 07 3 32 3 57 3 82 4 07 4 32 4 57 4 82 5 07 5 32 5 57 5 82 6 00 Rx2C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx2C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE FREQUENCY 70MHz TO 6GHz 11668 246 450 400 350 300 250 0 50 100 150 200 ZDIFF MAGNITUDE FREQUENCY GHz 0 07 0 32 0 57 0 82 1 07 1 32 1 57 1 82 2 ...

Page 68: ...th either a DC blocked differential PII network or a DC blocked differential T network The DC blocked differential T network is represented by the smaller box in Figure 48 The DC blocked differential PII network is represented by the larger box in Figure 48 The main advantages of the DC blocked differential PII network topology are a relatively wide impedance matching bandwidth up to 830 MHz and I...

Page 69: ...load impedance that represents the best compromise between the maximum output power delivered and the highest possible third order linearity OIP3 Load pull based impedance matching is very simple The focus is on developing the preferred load impedance at the Tx output ball pads This matching technique is quite different from the small signal techniques utilized for the Rx input Load pull Design th...

Page 70: ...figurations Figure 53 AD9361 Tx Output Differential Interface Configurations Figure 54 AD9361 Tx Output Differential Interface Configurations TXA_N TXA_P TX OUTPUT 1 3V CB 11668 052 TXA_N TXA_P TX OUTPUT 1 3V 1 3V 1 3V CB CC CC 11668 053 TXA_N TXA_P TX OUTPUT 1 3V 1 3V 1 3V CB 11668 054 TXA_N TXA_P TX OUTPUT 1 3V 1 3V 1 3V CB CC CC DRIVER AMPLIFIER 11668 055 Rev A ...

Page 71: ...lly a coupler is used to sample the power after the PA back into the Tx monitor input of the AD9361 device During this measurement transmit a typical burst A signal with constant power such as a preamble would give the most accurate results Once a single point measurement has been measured the Tx RSSI for other Tx power out levels can be calculated with the assumption that the assumption that the ...

Page 72: ... gain step calibration is only necessary if using the Rx RSSI feature and more detail on this calibration can be found in the Received Signal Strength Indicator RSSI section Tx POWER OUT VS Tx ATTENUATION AND Tx POWER OUT VS CARRIER FREQUENCY A factory calibration should be completed such that the output power of the system is known Depending on the linearity of the RF components chosen a single p...

Page 73: ...be set to 0x05 The BBP can also set more of the bits in Control Output Enable even if it does not monitor those signals Some of the signals are helpful in a production system while some others are useful for debug In either case Analog Devices recommends connecting the AD9361 control outputs to BBP inputs on the BBP so that the BBP can monitor real time conditions in the AD9361 Table 43 Control Ou...

Page 74: ... Syn VCO Tuning 8 Tx Synth VCO ALC 6 Tx Synth VCO ALC 5 Tx Synth VCO ALC 4 Tx Synth VCO ALC 3 Tx Synth VCO ALC 2 Tx Synth VCO ALC 1 Tx Synth VCO ALC 0 1C Rx Syn VCO Tuning 7 Rx Syn VCO Tuning 6 Rx Syn VCO Tuning 5 Rx Syn VCO Tuning 4 Rx Syn VCO Tuning 3 Rx Syn VCO Tuning 2 Rx Syn VCO Tuning 1 Rx Syn VCO Tuning 0 1D Tx Syn VCO Tuning 7 Tx Syn VCO Tuning 6 Tx Syn VCO Tuning 5 Tx Syn VCO Tuning 4 Tx ...

Page 75: ...al is low Control Output 4 Through Control Output 0 Always low 0x035 0x02 CALIBRATION BUSY Control Output 7 BB DC Cal Busy Normally low This signal is high only when the baseband DC calibration runs Control Output 6 RF DC Cal Busy Normally low This signal is high only when the RF DC calibration runs Control Output 5 CH1 Rx Quad Cal Busy Normally low This signal is high only when the Rx1 quadrature...

Page 76: ...g LMT Ovrg See 0x035 0x03 Control Output 2 Control Output 3 CH2 Lg ADC Ovrg See 0x035 0x03 Control Output 1 Control Output 2 CH2 Gain Lock Same as 0x035 0x04 Control Output 0 Control Output 1 CH2 Energy Lost This signal is normally low and applies only to the fast AGC It transitions high when the energy lost condition occurs and stays high as long as the condition is true Control Output 0 CH2 Stro...

Page 77: ...or the FDD state for FDD ENSM If the External Control Enable bit is set then in addition to being in the FDD State the BBP must turn on one or both transmitters via the TXNRX pin Control Output 3 CH2 RSSI Preamble Ready Same as Control Output 6 but applies to Rx2 Control Output 2 CH2 RSSI Symbol Ready Same as Control Output 5 but applies to Rx2 0x035 0x0A DIGITAL OVERFLOW Control Output 7 CH1 Tx I...

Page 78: ...BB DC CALIBRATION STATUS Control Output 4 BB DC Cal Busy This signal is high when the BB DC calibration runs If only the BB DC calibration is run then the signal will only be high once If an RF calibration only runs or if a BB DC calibration is run followed by an RF DC calibration the signal will be high for the BB DC calibration and then it will pulse high again during the RF DC calibration 0x035...

Page 79: ... is always true For AGC modes this signal will go low when the gain updates The pulse low occurs each time the gain update counter expires for the slow AGC or when Control Input 2 transitions high for hybrid mode Time duration of the low pulse is dependent on the AD9361 internal clock rates For the standard LTE 10 MHz profile the duration is approximately 400 ns In the fast AGC mode the signal wil...

Page 80: ...lliseconds is spent in State 1 Near the end of the calibration the state machine jumps to State 8 and then approximately 10 ms later it steps through State 0 through State 8 in approximately 200 µs remaining in State 8 after the calibration Control Output 3 Through Control Output 0 Tx Syn CP Cal 3 0 These signals represent the state of the transmitter charge pump calibration state machine However ...

Page 81: ...e profile the signal is high for approximately 40 ns Control Output 4 and Control Output 3 CH1 AGC State 1 0 See 0x035 0x0F Control Output 7 and Control Output 6 Control Output 2 CH1 Gain Change See 0x035 0x08 Control Output 4 Control Output 1 Temp Sense Valid This signal changes state when the temperature sensor word is valid The BBP can manually start a temperature measurement or it can set up t...

Page 82: ...s configured using the ad9361_auxdac_setup function By default the AuxDACs are disabled when the device is first powered up In certain applications it is desirable to delay the AuxDAC transition after the enable signal transitions Each AuxDAC has its own receive and transmit mode delay setting in Register 0x30 through Register 0x33 Each LSB equals approximately 1 µs Register 0x3A must be set based...

Page 83: ...er 0x1F D3 D0 To capture the voltage on the AUXADC pin the decimation filter clock should be routed on the CTRL_OUT0 pin To select the AuxADC decimation clock on the CTRL_OUT0 pin write Register 0x35 to Register 0x1E Data from Register 0x1E D7 D0 and Register 0x1F D3 D0 can be latched on the falling edge or on the rising edge of decimation clock coming out of the CTRL_OUT0 pin The SPI reads must o...

Page 84: ...mp Reading is set Data from register 0x0E can be latched into the baseband processor on the toggle of the temp sensor valid signal Bit D1 of Register 0x0C This signal should be routed out on the CTRL_OUT1 pin by writing 0x36 to Register 0x03 Figure 57 shows the temperature sweep of the AD9361 while reading the internal temperature sensor Table 46 specifies the register settings used to generate th...

Page 85: ...nd to state changes from Alert The upper nibble controls which GPO pins will change states when moving to Rx mode and the lower nibble controls which GPO pins will change states in Tx For example let Register 0x26 be 0x00 ENSM control enabled Register 0x27 be 0xFF initialize all GPO pins to 1 and Register 0x20 0x24 toggle the GPO_1 pin in Rx and GPO_2 in Tx When the part enters alert state all GPO...

Page 86: ...level of the GPO The off resistance of the GPO pins is 15 Ω The on resistance of the GPO pins is 32 Ω Table 47 Example Code for Auto Toggle Timing of GPO and AuxDAC Command Address hex Data hex Comment SPI Write 27 02 Set all GPOs to 0 except GPO_1 SPI Write 26 0 Set GPO to auto mode SPI Write 20 10 Set GPO_1 to 0 and GPO_0 to 1 in Rx SPI Write 29 0A GPO_1 delay 10 µs in Rx SPI Write 28 0A GPO_0 d...

Page 87: ...ator are required The AD9361 provides the capability to accept an external reference clock and synchronize operation with other devices using simple control logic Each AD9361 includes its own baseband PLL that generates sampling and data clocks from the reference clock input so an additional control mechanism is required to synchronize multiple devices A logical SYNC_IN pulse input is needed to al...

Page 88: ...o the same reference clock 6 Once the BBPLLs are synchronized clear the MCS BBPLL Enable bit and set the MCS Digital Clocks Enable bit while keeping the MCS BB Enable bits set This enables MCS to synchronize the digital clock dividers 7 After this register write input another rising edge pulse simultaneously to the SYNC_IN pin of each device This action synchronizes the data clock of each device t...

Page 89: ...chronized Figure 62 illustrates the DATA_CLK signals of two devices before and after the second SYNC_IN pulse occurs Note that the SYNC_IN pulse is much longer in duration than the DATA_CLK signals in this example As long as the setup and hold times meet the requirements listed in Figure 60 and Figure 61 this is an acceptable combination because the SYNC_IN input is edge detected by the REF_CLK re...

Page 90: ...mode is used Single ended CMOS logic compatibility is maintained Either one or both data ports may be utilized Using two ports allows for higher data throughput Both frequency division duplex FDD and time division duplex TDD operation are supported with one data port or two When LVDS mode is used Data port signaling is differential LVDS allowing up to 12 inch PCB traces connector interconnects bet...

Page 91: ...ree of over sampling and bandwidth mode FB_CLK FB_CLK is a feedback looped back version of DATA_CLK driven from the BBP to the FB_CLK_P pin in CMOS mode FB_CLK_N is left unconnected FB_CLK allows source synchronous timing with rising edge capture for the burst control signals TX_FRAME ENABLE and TXNRX FB_CLK also provides source synchronous timing with dual edge capture DDR or single rising edge c...

Page 92: ... number of cycles 0 before the ENABLE start pulse is sampled and it may be changed any number of cycles 0 after the ENABLE finish pulse is sampled It is important to note that the TXNRX signal should only change state while the ENSM is in the ALERT state because the TXNRX signal powers up and down the synthesizers directly in TDD mode In normal FDD mode the TXNRX signal is ignored but must be held...

Page 93: ...FB_CLK and D 11 0 allow the AD9361 to use FB_CLK to capture the data A data transfer starts when the ENABLE signal pulses or goes high and the end of the data transfer is marked but another pulse on the ENABLE line or when it returns low The direction of data transfer is determined by the TXNRX signal When this signal is low and the ENSM is in the Rx or FDD state the bus is configured in the recei...

Page 94: ...e fixed constant values or the preceding data sample values can be repeated to reduce the bus switching factor and therefore power consumption SINGLE PORT TDD FUNCTIONAL TIMING CMOS The timing diagrams in Figure 65 and Figure 66 illustrate the relationship among the bus signals in single port TDD mode These diagrams show an example of timing for both SDR and DDR modes of operation For all subseque...

Page 95: ...0 R1_I 11 0 R1_Q 11 0 R2_I 11 0 R2_Q 11 0 2R2T DDR TDD SINGLE PORT 0x010 0xC8 0x011 0x00 0x012 0x0C 2R2T DDR TDD SINGLE PORT 0x010 0xC8 0x011 0x00 0x012 0x0C R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 DNC DNC DNC DNC DNC DNC R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 ...

Page 96: ...2T DDR TDD SINGLE PORT 0x010 0xC8 0x011 0x00 0x012 0x0C 2R2T DDR TDD SINGLE PORT 0x010 0xC8 0x011 0x00 0x012 0x0C T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 DNC DNC DNC DNC DNC DNC T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 T1_I 11 0 T1_Q 11 0 1R2T DDR TDD SINGLE PO...

Page 97: ...with a 50 duty cycle until the data transfer is complete Similarly Tx_FRAME accepts either format from the BBP The transmit data samples are carried in two s complement format with the first 6 bit byte P0_D 11 6 containing the MSBs and the second 6 bit byte P0_D 11 6 containing the LSBs P0_D 11 is the numerically most significant bit and P0_D 6 is the least significant bit The receive data samples...

Page 98: ...ence Manual Page 98 of 128 Figure 67 Single Port Full Duplex Mode DATA_CLK RX_FRAME P0_D 11 6 FB_CLK TXNRX ENABLE RX DATA RX DATA TX DATA TX DATA CTRL CTRL PLL FEEDBACK CLK GEN AD9361 BBP TX_FRAME P0_D 5 0 11668 068 Rev A ...

Page 99: ...1_Q 11 6 R1_I 5 0 R1_I 5 0 1R1T DDR FDD SINGLE PORT 0x010 0xC8 0x011 0x00 0x012 0x04 11668 069 DATA_CLK RX_FRAME P0_D 5 0 P1_D 5 0 R1_I 11 6 R1_Q 11 6 R1_I 5 0 R1_I 5 0 R1_I 11 6 R1_Q 11 6 R1_I 5 0 R1_I 5 0 R1_I 11 6 R1_Q 11 6 R1_I 5 0 R1_I 5 0 2R2T DDR FDD SINGLE PORT 0x010 0xC8 0x011 0x00 0x012 0x04 FB_CLK TX_FRAME P0_D 11 6 P1_D 11 6 T1_I 11 6 T1_Q 11 6 T1_I 5 0 T1_I 5 0 T1_I 11 6 T1_Q 11 6 T1_...

Page 100: ... pulse on the ENABLE line or when it returns low The direction of data transfer is determined by the TXNRX signal When this signal is low and the AD9361 is in the FDD state or the Rx state the ENSM configures the bus in the receive direction data transferred from AD9361 to BBP All other states result in the bus being set to high impedance When TXNRX is driven high the ENSM changes the bus to the t...

Page 101: ...ystem with only the Tx Channel 1 used the Tx burst would have two unused slots as follows The AD9361 captures P0 I1 X I1 X P1 Q1 X Q1 X The unused X slots can be filled with arbitrary data values by the BBP Such values can be either constant values or the preceding data sample values can be repeated to reduce the bus switching factor and therefore power consumption DUAL PORT TDD FUNCTIONAL TIMING ...

Page 102: ...0x00 0x012 0x08 T1_I 11 0 T1_I 11 0 T1_I 11 0 T1_I 11 0 T1_I 11 0 T1_I 11 0 T1_Q 11 0 T1_Q 11 0 T1_Q 11 0 T1_Q 11 0 T1_Q 11 0 T1_Q 11 0 11668 272 FB_CLK TX _FRAME P0_D 11 0 P1_D 11 0 2R2T DDR TDD DUAL PORT 0x010 0xC8 0x011 0x00 0x012 0x08 T1_I 11 0 T2_I 11 0 T1_I 11 0 T2_I 11 0 T1_I 11 0 T2_I 11 0 T1_Q 11 0 T2_Q 11 0 T1_Q 11 0 T2_Q 11 0 T1_Q 11 0 T2_Q 11 0 0 0 0 0 Rev A ...

Page 103: ...to have a rising edge at the beginning of each frame and repeat with a 50 duty cycle until the data transfer is complete Similarly Tx_FRAME accepts either format from the BBP The Tx data samples are carried in two s complement format P1_D 11 is the numerically most significant bit and P1_D 0 is the least significant bit The Rx data samples are also carried in two s complement format P0_D 11 is the...

Page 104: ...RAME P 0_D 11 0 1R1T DDR FDD DUAL PORT 0X010 0XC8 0X011 0X00 0X012 0X02 2R2T DDR FDD DUAL PORT 0X010 0XC8 0X011 0X00 0X012 0X02 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 R1_I 11 0 R1_Q 11 0 11668 075 FB _CLK TX_FRAME P0_D 11 0 FB _CLK TX_FRAME P0_D 11 0 1R1T DDR FDD DUAL PORT 0X010...

Page 105: ...hold time from FB_CLK at AD9361 inputs ENABLE TXNRX tSTx 1 ns Tx data setup time to FB_CLK at AD9361 inputs tHTx 0 ns Tx data hold time from FB_CLK at AD9361 inputs tDDRx 0 ns 1 5 ns 1 2 ns Rx data delay from DATA_CLK to D 11 0 outputs 1 8 V supply Rx data delay from DATA_CLK to D 11 0 outputs 2 5 V supply tDDDV 0 ns 1 0 ns Rx data delay from DATA_CLK to Rx_FRAME tENPW tCP ENABLE pulse width edge ...

Page 106: ... The AD9361 LVDS interface facilitates connecting to custom ASICs and FPGAs that have LVDS capability LVDS interfaces are typically used when a system needs superior switching performance in noisy environments and higher data rates than a standard CMOS interface can provide When utilizing LVDS mode it is recommended to keep all trace lengths no longer than 12 inches and to keep differential traces...

Page 107: ...ata samples provided by the BBP A high transition indicates the beginning of the frame Tx_FRAME can accept a single high transition at the beginning of a burst that stays high throughout the burst or a pulse train that has a rising edge at the beginning of each frame 50 duty cycle The AD9361 transmits null data all zeros until the first Tx_FRAME indicates valid data This is a useful feature when t...

Page 108: ... controls the Tx function In this mode called FDD independent control mode the BBP independently controls the Tx function which can result in power consumption savings LVDS MAXIMUM CLOCK RATES AND SIGNAL BANDWIDTHS The data listed in Table 50 compares the maximum data clock rates and signal bandwidths in the different allowable operating modes for the LVDS data bus configuration Maximum RF band wi...

Page 109: ...are time interleaved on each data bus For a 1R1T system the I and Q samples are carried in a 4 way interleave IMSB QMSB ILSB QLSB For this case the Tx_FRAME and Rx_FRAME signals are coincident with data switching Each is in a high state for IMSB and QMSB and a low state for ILSB and QLSB when 50 duty cycle framing is enabled These signals then switch high again with IMSB to indicate the start of a...

Page 110: ... 0 R2_I 11 6 R2_Q 11 6 R2_I 5 0 R2_Q 5 0 R2_I 11 6 R2_Q 11 6 R2_I 5 0 R2_Q 5 0 R1_I 11 6 R1_Q 11 6 R1_I 5 0 R1_Q 5 0 R1_I 11 6 R1_Q 11 6 R1_I 5 0 R1_Q 5 0 FB_CLK_P TX_FRAME_P TX_D 5 0 _P TX_D 5 0 _N FB_CLK_N TX_FRAME_N 1R1T DDR FDD LVDS 0x010 0xC8 0x011 0x00 0x012 0x10 T_I 11 6 T_Q 11 6 T_I 5 0 T_Q 5 0 T_I 11 6 T_Q 11 6 T_I 5 0 T_Q 5 0 T_I 11 6 T_Q 11 6 T_I 5 0 T_Q 5 0 T_I 11 6 T_Q 11 6 T_I 5 0 T_...

Page 111: ... for the LVDS data buses Table 51 Data Path Timing Constraint Values LVDS Mode Parameter Min Typ Max Description tCP 4 069 ns DATA_CLK cycle time clock period tMP 45 of tCP 55 of tCP DATA_CLK and FB_CLK high and or low minimum pulse width including effects of duty cycle distortion period jitter cycle cycle jitter and half period jitter tSTx 1 ns Tx_D 5 0 Tx_FRAME setup time to FB_CLK falling edge ...

Page 112: ...Timing Parameter Diagrams LVDS Bus Configuration I_M Q_M Q_M I_M Q_L I_L Q_L I_L Q_L I_L I_L Q_L I_M Q_M I_L Q_L DATA_CLK_P DATA_CLK_N RX_FRAME_P RX_FRAME_N RX_D 5 0 TX_FRAME_N TX_FRAME_P FB_CLK_P FB_CLK_N TX_D 5 0 tMP tCP tDDDV tDDRX tMP tCP tSTX tHTX 11668 082 Rev A ...

Page 113: ...SP_DI is used as a bidirectional data signal that both receives and transmits serial data In 3 wire configuration this signal is referred to as SP_DIO in this section to distinguish between the two configurations The data signals are launched on the rising edge of SPI_CLK and sampled on the falling edge of SPI_CLK by both the BBP and the AD9361 SPI_DI or SPI_DIO carries the control field from BBP ...

Page 114: ... with the starting byte address of 0x02A After the first data byte is written the internal byte address generation logic decrements to 0x029 which is the destination of the second byte After the second byte is written the internal byte address generation logic decrements to 0x028 which is the destination of the third byte After the third byte is written the internal byte address generation logic d...

Page 115: ..._CLK cycle time clock period tMP 9 ns SPI_CLK pulse width tSC 1 ns SPI_ENB setup time to first SPI_CLK rising edge tHC 0 ns Last SPI_CLK falling edge to SPI_ENB hold tS 2 ns SPI_DI data input setup time to SPI_CLK tH 1 ns SPI_DI data input hold time to SPI_CLK tCO 3 ns 8 ns SPI_CLK rising edge to output data delay 3 wire or 4 wire mode tHZM tH tCO max Bus turnaround time after BBP drives the last ...

Page 116: ... EN_AGC EN_AGC is an input signal that provides real time control of when the AGC is active When pulled high the EN_AGC pin forces the AGC to unlock so that adjustments to the gain setting can be made If the EN_AGC pin is not used then the Gain Lock Delay bit must be set high GPO 3 0 The GPO pins are digital outputs that can be configured to monitor the status of the ENSM or serve as general purpo...

Page 117: ... any splits under the RF traces Layer 2 and Layer 9 are crucial to maintaining the RF signal integrity and therefore the AD9361 performance Layer 3 and Layer 8 contain the 1 3 V analog supply the 3 3 V GPO supply and the 1 8 V VDD_INTERFACE supply To keep the RF section of the AD9361 isolated from the fast transients of the digital section the digital lines from the AD9361 are on inner Layer 5 and...

Page 118: ...pled The system designer can optimize the RF performance with a proper selection of the balun and the ac coupling capacitors The Tx monitor traces external LO traces and the external clock traces could require matching components as well to ensure best performance All the previous RF signals mentioned must have a solid ground reference under them None of the critical traces should run over a secti...

Page 119: ...trace from the BGA land pad and drop the digital signals on the inner layers by using a 6 mil via with a 12 mil keep out The spacing between the BGA lands to the pin escape via is 22 mils Once the signal is on the inner layers a 4 9 mil trace 50 Ω connects the signal to the FPGA The recommended BGA land size is 14 mills Only one signal trace is routed between adjacent BGA land pads and between pin...

Page 120: ... to be at least a 0 1 µF bypass capacitor near each power supply ball Install 10 µF bypass capacitor on the VDDA1P3_RX_SYNTH J3 and VDDA1P3_TX_SYNTH K3 ball Install a 10 µF capacitor near the Tx balun DC feed POWER MANAGEMENT AND SYSTEM NOISE CONSIDERATIONS The AD9361 has three different power domains on the chip 1 3 V is the main power domain that powers the major part of the chip The VDD_INTERFA...

Page 121: ...ADP1755 Power Up 1 3 V Analog Supply on the AD9361 with Switching Regulator Using a switching regulator to power the AD9361 provides great efficiency that is easily transferrable to an overall cost reduction A switching regulator can power the 1 3 V analog power supply of the AD9361 However choosing the right switching regulator is crucial to getting the best performance from the AD9361 During the...

Page 122: ...ferred as this reduces low frequency sidebands that can fall below 1 MHz Maximum Output Capacitance In switching regulators with limitation for the maximum allowable output capacitance it is important to consider the effects over the lowest frequency that can be decoupled from the power supply noise Two main factors affect the transient response of a switching regulator the output capacitor ESR an...

Page 123: ...lator frequency is 5 8 GHz This is because the synthesizer always generates a frequency between 6 GHz to 12 GHz To generate a specific LO the synthesizer output is divided which also reduces the noise spectrum Conversely the highest frequency designs require the lowest amount of power supply noise because the divide ratios are small Figure 90 shows the best performance when the ADP1755 LDO is used...

Page 124: ...D2 VDDA1P3_RX_RF Short to D3 Power supply for the Rx LNAs and the mixer GM stages D3 VDDA1P3_RX_TX Short to E3 Power supply for Tx Low pass filter Tx monitor Rx trans impedance amplifier Rx low pass filter AuxDAC E2 VDDA1P3_RX_LO Short to F2 Power supply for Rx LO generator and LO divider E3 VDDA1P3_TX_LO_BUFFER 1 3 V separate trace to common supply point Power supply to the Tx LO buffer that goes...

Page 125: ...1P3_RX_VCO_LDO VDDA1P3_TX_LO VDDA1P3_TX_VCO_LDO can be powered up with a separate low noise LDO This will also help in mitigating effects of transients on the 1 3 V analog supply The evalua tion board uses this power design Tx Balun DC Feed Supplies Each transmitter requires 150 mA of current that the DC feed of the balun supplies To reduce switching transients when attenuation settings change the...

Page 126: ...onment simulates the worst case VCO frequency deviation that can occur on the Rx synth The blue trace in Figure 93 shows the voltage transient on the 1 3 V line when the transmitters turn ON The magenta trace is the Vtune voltage of the Tx VCO that is probed on the Tx EXT LO line and the green trace is the Vtune voltage of the Rx VCO that is probed on the Rx EXT LO line The instantaneous frequency...

Page 127: ...ous Frequency Deviation Seen Due to a Voltage Transient on the 1 3 V Supply VDDA1P3_Rx_SYNTH VDDA1P3_Tx_SYNTHs Supplied Externally 11668 293 VTUNE VOLTAGE OF THE TX VCO THAT IS PROBED ON THE TX EXT LO LINE VOLTAGE TRANSIENT ON THE 1 3V LINE WHEN THE TRANSMITTERS TURN ON VTUNE VOLTAGE OF THE RX VCO THAT IS PROBED ON THE RX EXT LO LINE 11668 095 Rev A ...

Page 128: ...may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality LegalTermsandConditions Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties th...

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