XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 34 - http://www.acromag.com
- 34 -
www.acromag.com
PCIe AXI-Bridge Control
The PCIe AXI bridge is an interface between the AXI4 and the PCIe. This
bridge provides the translation level between the AXI4 memory-mapped
embedded system to the PCIe system. The AXI Bridge for PCIe translates the
AXI4 memory read or writes to PCIe Transaction Layer Packets (TLP) packets
and translates PCIe memory read and write request TLP packets to AXI4
interface commands.
Table 3.17:
PCIe AXI Bridge
Control Registers
BAR0 Base Addr+
Bit(s)
Description
0x000F0000→
0x000F0140
31:0
See Xilinx DS820 Memory Map
0x000F0144
31:0
Physical Side Interface Status
0x000F0148→
0x000F0204
31:0
See Xilinx DS820 Memory Map
0x000F0208
31:0
Address Translation Register Upper
AXIBAR2PCIEBAR_0U
0x000F020C
31:0
Address Translation Register Lower
AXIBAR2PCIEBAR_0L
0x000F0210→
0x000F0FFF
31:0
See Xilinx DS820 Memory Map
Physical Side Interface Status/Control Register (Read/Write) - (BAR0 + 0x000F0144)
This register provides the status of the current PHY state, as well as control
of speed and rate switching for Gen2-capable cores.
Table 3.18:
CDMA Control
Register
Bit(s)
FUNCTION
0
Reports the current link rate.
0
2.5 GT/s
1
5.0 GT/s
2-1
Reports the current link width.
00
x1
01
x2
10
x4
11
x8
8-3
Reports the current Link Training and Status State Machine
state. Encoding is specific to the underlying Integrated Block.
x
x
10-9
Reports the current lane reversal mode.
00
No reversal
01
Lanes 1:0 reversed
10
Lanes 3:0 reversed
11
Lanes 7:0 reversed
