XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 105 - http://www.acromag.com
- 105 -
www.acromag.com
Board Oscillators
Board Crystal Oscillators:
125MHz (U21, U31)
Frequency Stability
: ± 0.00315% or 31.5ppm
Board Crystal Oscillator:
200MHz (U3)
Frequency Stability
: ± 0.00315% or 31.5ppm
Board Crystal Oscillator:
48MHz (U3)
Frequency Stability
: ± 0.0050% or 50ppm
DDR3 Memory
128 Meg x 16-bit
Micron Device MT41J128M16HA-15EIT uses a double data
rate architecture.
Four MT41J128M16HA-15EIT memory devices (U8, U9, U10 and U11) are
used to form a 64-bit data bus.
128 Meg x 16-bit =2Gb
each device
8Gb = 1GB total
all four devices together
DDR3 memory devices are wired to FPGA banks 15, 16, 26, and 36.
DCI VRP/N resistor connections are implemented on banks 15 and 36.
DCI functionality in bank 15 is achieved in the UCF by cascading DCI between
adjacent banks as follows:
CONFIG DCI_CASCADE = “15 16”;
The memory interface logic require a set of FPGA “No Connect” pins. These
are found in the UCF as CONFIG PROHIBIT pins as follows:
CONFIG PROHIBIT = A16,D34,F33,K16,K26,L15,N28,N33;
CONFIG PROHIBIT = F31,K14;
QDR II+ SRAM Memory
Two CY7C1565KV18-400BZI memory devices (U12 and U13) are used to
form a 72-bit data bus.
2 Meg x 36-bit
Cypress CY7C1565KV18-400BZI memory QDR II+ are
synchronous pipelined Burst SRAMs equipped with separate read and write
ports.
2 Meg x 36-bit =72Mb
each device
144Mb = 18MB total
both devices together
