XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 55 - http://www.acromag.com
- 55 -
www.acromag.com
PCI INTERFACE LOGIC
The Acromag example design PCIe bus interface logic on this board provides
a 2.5Gbps interface to the carrier/CPU board per PCI Express Specification
v2.0. The interface to the carrier/CPU board allows control of example
design board functions.
The PCIe bus endpoint interface logic is contained within the Virtex 6 FPGA.
This logic includes support for PCIe commands, including: configuration
read/write, and memory read/write. In addition, the PCIe interface
requester and or completion accesses. Payload of up to 256 bytes is
supported.
The logic also implements interrupt requests via message signaled
interrupts. Messages are used to assert and de-assert virtual interrupt lines
on the link to emulate the Legacy PCI interrupt INTA# signal.
DDR3 Memory
A 128 Meg x 64-bit of DDR3 memory is provided for user applications. Four
DDR3 memory devices are used to form a 64-bit data bus. Each of the
devices (U8, U9, U10 and U11) are 128 Meg x 16 bit (2Gb) in size. All four
device add to 8Gb or 1GByte total memory. The DDR3 interface is
implemented in FPGA banks 15, 16, 26, and 36. DCI VRP/N resistor
connections are implemented on banks 15 and 36. DCI functionality in bank
15 is achieved in the UCF by cascading DCI between adjacent banks as
follows:
CONFIG DCI_CASCADE = “15 16”;
The memory interface logic requires a set of FPGA “No Connect” pins.
These are found in the UCF as CONFIG PROHIBIT pins as follows:
CONFIG PROHIBIT = A16,D34,F33,K16,K26,L15,N28,N33;
CONFIG PROHIBIT = F31,K14;
On board termination devices are provided at the DDR3 device for
termination of the address and data as received from the FPGA.
QDR II+ SRAM Memory
A 2 Meg x 72-bit or 16MB of QDRII+ SRAM memory is provided for user
applications. Two QDRII+ memory devices are used to form a 72-bit data
bus. Each of the devices (U12 and U13) are 2 Meg x 36 bit (72Mb) is size.
Both QDR device together total 144Mb or 18MBytes. The QDRII+ interface
is implemented in FPGA banks 13, 22, 23, 32 and 33. DCI VRP/N resistor
connections are implemented on bank 22. DCI functionality in bank 23 is
achieved in the UCF by cascading DCI between adjacent banks as follows:
CONFIG DCI_CASCADE = “22 23”;
