XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 63 - http://www.acromag.com
- 63 -
www.acromag.com
feature of the Xilinx AXI-CDMA core. Because of a limitation in the Xilinx AXI
Interconnect, it is not possible to connect buses larger than 32 bits to the
PCIe control bus (where PCIe registers reside). AXI PCIe control bus is an
AXI4 Lite protocol and can only support single 32 bit transactions. The AXI
CDMA bus is an AXI4 Full protocol capable of bursts of various lengths. (see
“AMBA AXI Protocol Specification” for further details).
For some users, it may be desirable to use Scatter-Gather mode, in which
case a descriptor list can be set up in QDR memory to move data to or from
host memory. In order for the AXI CDMA core to move data from the QDR
memory to or from host memory, it must first write the base address
translation registers in the AXI PCIe core with an address translation. In this
mode, the AXI CDMA would need to be connected to the AXI PCIe Control
Bus but the data width of the CDMA bus must be set to 32 bits.
However, if Scatter-Gather is not essential, it can be disabled and the data
width of the AXI CDMA can be set to 64 bits (or larger) to improve through-
put.
Acromag includes both Scatter-Gather and no Scatter-Gather versions of the
projects to illustrate both examples.
