Acromag XMC-6VLX Series, User Manual

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XMC-6VLX USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 - 20 - http://www.acromag.com - 20 - www.acromag.com
The ISR register is writable by software only until the Hardware Interrupt
Enable bit in the MER has been set. Given these restrictions, when this
register is written to, any data bits that are set to ‘1’ will activate the
corresponding interrupt just as if a hardware input became active. Data bits
that are zero have no effect. This allows software to generate interrupts for
test purposes.
Interrupt Pending Register (Read) - (BAR0 + 0x00100004)
This Interrupt Pending register (IPR) at BAR0 base a offset 0x100004
is used to monitor board interrupts. Reading the contents of this register
indicates the presence or absence of an active interrupt signal that is also
enabled. Each bit in this register is the logical AND of the bits in the
Interrupt Status register and the Interrupt Enable register.
Table 3.5: Interrupt Pending
Register
Bit(s) FUNCTION
0
This bit when set indicates a Xilinx Fabric interrupt from the
Front I/O interface. See the Front I/O interrupt section for
source of this interrupt.
0 Disabled
1 Enabled
1
This bit when set indicates an AXI CDMA interrupt. See the
CDMA section for source of this interrupt.
0
Disabled
1
Enabled
31-2
Reserved
0 NA
1 NA
Interrupt Enable Register (Read/Write) - (BAR0 + 0x00100008)
This is a read/write register. Writing a ‘1’ to a bit in this register enables the
corresponding Interrupt Status bit to cause assertion of the interrupt output.
This Interrupt Enable bit set to ‘0’ does not inhibit an interrupt condition
from being captured. It will still show up in the Interrupt Status register even
when not enabled here. To show up in the Interrupt Pending register it
needs to be enabled here. Writing a ‘0’ to a bit disables, or masks, the
generation of interrupt output for the corresponding interrupt input signal.
Note however, that disabling an interrupt input is not the same as clearing it.
Disabling an active interrupt prevents that interrupt from reaching the IRQ
output. When it is re-enabled, the interrupt immediately generates a
request on the IRQ output. An interrupt must be cleared by writing to the
Interrupt Acknowledge Register, as described below. Reading this Interrupt
Enable register indicates which interrupt inputs are enabled; where a ‘1’
indicates the input is enabled and a ‘0’ indicates the input is disabled.