XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 67 - http://www.acromag.com
- 67 -
www.acromag.com
Acromag Peripheral Repository
Acromag has modified a few of the Xilinx supplied peripheral cores or
created custom cores to support XMC-V6 specific requirements. The
following cores are included in the pcore_subdirectory: axi_ethernet,
axi_pcie, axi_enhanced_pcie, axi_to_qdr_mc, util_bufr_core, axi_cdma,
util_ds_buf and util_ds_buf_mgtclk. These are used in the example design
and will take priority over the Xilinx cores because of the “Project Peripheral
Repository Search Path” option in the “Project Options” menu of the ISE tool
points to this repository.
Modifications to the AXI
Ethernet Core
The AXI Ethernet pcore supplied by Xilinx includes a regional clock buffer
instantiated in a lower level of the hierarchy. This is okay when a single
instance of the pcore is included in the design, but the XMC-V6 has two
Ethernet ports that must be located in the same clock region. There is only
one regional clock buffer available in a region, so instantiating two of the
Xilinx supplied axi_ethernet pcores resulted in a map error. The regional
clock buffer had to be moved from the lower level to the top level so that it
could be shared between two instances of axi_ethernet. The pcore is
configured for a 1000Base-X physical interface at 1 Gbs. This configuration
is compatible with both the 1000Base-X and the 1000Base-T SFP modules
available from Acromag.
util_bufr_core Core
A pcore was created to instantiate a regional clock buffer in XPS. This clock
buffer was required by the modified axi_ethernet pcore.
util_buf_ds_mgtclk Core
A pcore was created to instantiate an IBUFDS_GTXE1 clock buffer in XPS.
This clock buffer was required by the modified axi_ethernet pcore.
AXI QDRII+ Memory Controller
Xilinx did not provide a complete AXI interface (in ISE 14.1) to the memory
controller when it is configured for a QDR II+ application. Acromag has
provided the missing functionality. This AXI QDR II+ pcore has separate 256
bit read and write interfaces. It supports continuous simultaneous 125 MHz
read and write bursts.
Modifications to the CDMA
Core
Fixed a bug in the TCL script that failed to close an output file upon
termination (in ISE 14.1). The supported devices list was modified to include
only the Virtex 6.
Modifications to the AXI PCIe
Core
Modifications to the AXI PCIe core were necessary to separate the reset
from the rest of the AXI system. When resetting the AXI system, form
example through MicroBlaze, the PCIe configuration space would also be
reset preventing the host from communicating with the FPGA through the
AXI PCIe core until a power-cycle of the board was done. The
axi_enhanced_pcie core is a Xilinx “helper core” for the AXI PCIe core and
was modified to bring the 250MHz clock to the top level which was
generated by a MMCM internal to this core.
