XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 7 - http://www.acromag.com
- 7 -
www.acromag.com
provides LVCMOS single ended signaling.
Interface to Mezzanine Connector –
The Virtex 6 FPGA is directly
connected to a front mezzanine connector. All 2.5volt IO standards
supported by the Virtex 6 device are available on 13 signal pairs. JTAG
for Virtex 6 configuration and use with Xilinx ChipScope FPGA signal
analysis tool. USB is provides a MicroBlaze debug terminal port. Two
high speed serial interfaces are also routed from the FPGA to this
mezzanine module connector.
Example Design Provided –
The example VHDL design includes
implementation of the PCIe bus 4 lane Gen 1, control of digital front and
rear I/O, and QDRII read/write interface logic, SFP module interface for
1 Gig Ethernet with DDR3 Memory.
PCle Interface Features
PCIe Bus –
An example design is provided with four lane PCI Express
Generation 1 operating at a bus speed of 2.5 Gbps per lane per
direction. This gives up to 2GBytes/sec data rate on the bus. FPGA
supports Gen1 8-lane (x8) or Gen2 4-lane (x4).
PCIe Bus Master –
The PCIe interface logic becomes the bus master to
perform DMA transfers.
DMA Operation –
The PCIe bus interface supports one DMA channel
capable of transferring data to and from the on board QDRII SRAM.
Compatibility
– PCI Express Base Specification v2.0 compliant PCI
Express Endpoint. Provides one multifunction interrupt. The XMC-6VLX
is compatible with XMC VITA 42.3 specification for P15.
