XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 19 - http://www.acromag.com
- 19 -
www.acromag.com
INTERRUPT CONTROLLER
The AXI Interrupt Controller concentrates multiple interrupt inputs from
peripheral devices to a single interrupt output to the system processor using
the PCIe bus. The interrupt controller contains programmer accessible
registers that allow interrupts to be enabled, queried and cleared under
software control over the PCIe bus interface.
Table 3.3:
Interrupt Controller
Registers
Note that any registers/bits not
mentioned will remain at the
default value logic low.
BAR0 Base Addr+
Bit(s)
Description
0x00100000
31:0
Interrupt Status Register
0x00100004
31:0
Interrupt Pending Register
0x00100008
31:0
Interrupt Enable Register
0x0010000C
31:0
Interrupt Acknowledge Register
0x00100010
31:0
Set Interrupt Enable Register
0x00100014
31:0
Clear Interrupt Enable Register
0x00100018
31:0
Interrupt Vector Register
0x0010001C
31:0
Master Enable Register
Interrupt Status Register (Read/Write) - (BAR0 + 0x00100000)
This Interrupt Status register (ISR) at BAR0 base a offset 0x100000 is
used to monitor board interrupts. When read, the contents of this register
indicate the presence or absence of an active interrupt for each of the active
interrupting sources. Each bit in this register that is set to a ‘1’ indicates an
active interrupt signal on the corresponding interrupt input. Bits that are
‘0’are not active. The bits in the ISR are independent of the interrupt enable
bits in the Interrupt Enable register. Interrupts, even if not enabled can still
show up as active in the ISR.
Table 3.4:
Interrupt Status
Register
Bit(s)
FUNCTION
0
This bit when set indicates a Xilinx Fabric interrupt from the
Front I/O interface. See the Front I/O interrupt section for
source of this interrupt.
0
Disabled
1
Enabled
1
This bit when set indicates an AXI CDMA interrupt. See the
CDMA section for source of this interrupt.
0
Disabled
1
Enabled
31-2
Reserved
0
NA
1
NA
