XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 5 - http://www.acromag.com
- 5 -
www.acromag.com
RELATED PUBLICATIONS
The following manuals and part specifications provide the necessary information for in depth understanding of
the XMC-6VLX board.
Virtex-6 Data Book Spec
http://www.xilinx.com
CY7C1565KV18-400BZC Spec.
http://www.cypress.com
MT41J128M16HA-15EIT Spec.
http://www.micron.com
1.0 GENERAL INFORMATION
This XMC-6VLX is an XMC module with the heart of the design being the
Virtex 6 reprogrammable FPGA
.
The re-configurable XMC-6VLX modules
use the Xilinx Virtex 6 XC6VLX FPGA. Re-configuration of the FPGA is
possible via a direct download into the Xilinx Platform Flash over the PCIe
bus. The on board Platform Flash memory loaded with FPGA configuration
data allows automatic Xilinx configuration on power-up.
The XMC-6VLX is an XMC module with the following interfaces. Eight high
speed serial lanes are allocated to the XMC P15 connector. These lanes can
be used for an 8 lane PCIe (PCI Express) implementation, Serial RapidIO, or
10 Gigabit Ethernet. The example design will support a 4 lane Gen 1 PCIe
implementation with one DMA channel for data transfer between PCIe and
on board QDRII memory.
Eight high speed serial lanes are also allocated to the XMC P16 connector.
These eight serial lanes can be used for Serial RapidIO, PCIe, 10 Gigabit
Ethernet, or Xilinx Aurora. The example design will support an 8 lane Aurora
implementation for use of these lanes. Two Virtex 6 global clocks and 34
select I/O signals will also be provided on the P16 connector. Select I/O
signals are 2.5V Virtex 6 I/O pins that can be selected from single-ended I/O
standards (LVCMOS, HSTL, and SSTL) and differential I/O standards (LVDS,
HT, LVPECL, BLVDS, Differential HSTL and SSTL).
One P4 rear I/O connector will provide two global clock differential pairs,
and 30 LVDS signal pairs.
One mezzanine connector will provide JTAG, USB signals, two global
differential clock pairs, 11 LVDS signal pairs, and two ground signals. Two
high speed serial interfaces are also routed from the FPGA to this mezzanine
module connector.
The board will provide 2 Meg x 72-bit QDRII SRAM, 128 Meg x 64-bit DDR3
SDRAM, 4 Meg x 16-bit parallel Flash, and Xilinx 128 Megabit Platform Flash.
The parallel Flash will interface to the FPGA for MicroBlaze CPU program
