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XMC-6VLX

USER’S MANUAL

Acromag, Inc. Tel: 248-295-0310

- 6 - http://www.acromag.com

- 6 -

www.acromag.com

Ordering Information

The following table lists the orderable models and their corresponding
operating temperature range.

Models XMC-6VLX240 and XMC-6VLX365 are conduction-cooled without
front I/O.

Table 1.1:

The XMC-6VLX

boards are available in the
standard temperature range

.

MODEL

OPERATING TEMPERATURE RANGE

XMC-6VLX240

0



C to +70



C

XMC-6VLX365

0



C to +70



C

Key Features

An XMC-6VLX block diagram, found at the end of this manual, illustrates the
key features listed below.



Reconfigurable Xilinx FPGA –

In system configuration of the FPGA is

performed through flash configuration. The PCIe bus can be used to
change the flash configuration memory. This provides a means for
creating custom user defined designs. The Virtex 6 will configure from
the updated Platform flash on the next power cycle.



QDRII SRAM –

Provides 2 Meg x 72-bit QDRII SRAM. SRAM is linked to

the Virtex 6 device for PCIe bus, and DMA engine access. It can also be
linked to front, rear, and high speed data path access.



DDR3 SDRAM –

Provides 128 Meg x 64-bit DDR3 SDRAM. SDRAM is

linked to the Virtex 6 device for MicroBlaze and Ethernet access.



P15 High Speed Interface –

The Eight high speed serial lanes are

allocated to the XMC P15 connector. These lanes can be used for an 8
lane PCIe (PCI Express) implementation, Serial RapidIO, or 10 Gigabit
Ethernet. The example design will support a 4 lane Gen 1 PCIe
implementation.



P16 High Speed Interface –

The Eight high speed serial lanes are

allocated to the XMC P16 connector. These lanes can be used for Serial
RapidIO, PCIe, 10 Gigabit Ethernet, or Xilinx Aurora. The example design
will support an 8 lane Aurora loopback implementation.



Interface to Rear P4 Connector –

The Virtex 6 FPGA is directly

connected to 64 pins of the rear P4 connector. All 2.5volt IO standards
supported by the Virtex 6 device are available. The example design

code storage. The Xilinx 128 Megabit Platform Flash will contain the power
up configuration bit file for the Virtex 6 FPGA.

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Summary of Contents for XMC-6VLX Series

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...GA XMC Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 295 0310 Copyright 2012 Acromag Inc Printed in the USA Data and specifications are...

Page 3: ...ATION FOR USE 9 Unpacking and Inspecting 9 Card Cage Considerations 9 Heat Sink Considerations 9 Board Installation 9 Default Hardware Configuration 10 P16 Secondary XMC Connector 10 Rear P4 Field I O...

Page 4: ...XI BAR0 Aperture Base Address 33 PCIe AXI Bridge Control 34 Physical Side Interface Status Control Register Read Write BAR0 0x000F0144 34 AXI Base Address Translation Configuration Register Read Only...

Page 5: ...R Memory Read Write BAR2 0x0000000 to 0x00FFFFFF 53 4 0 THEORY OF OPERATION 54 PCI INTERFACE LOGIC 55 DDR3 Memory 55 QDR II SRAM Memory 55 Clock Generation 56 Multi Gigabit Transceivers GTX MGTs 56 SF...

Page 6: ...You must consider the possible negative effects of power wiring component sensor or software failure in the design of any type of control or monitoring system This is very important where property los...

Page 7: ...e example design will support a 4 lane Gen 1 PCIe implementation with one DMA channel for data transfer between PCIe and on board QDRII memory Eight high speed serial lanes are also allocated to the X...

Page 8: ...SRAM SRAM is linked to the Virtex 6 device for PCIe bus and DMA engine access It can also be linked to front rear and high speed data path access DDR3 SDRAM Provides 128 Meg x 64 bit DDR3 SDRAM SDRAM...

Page 9: ...ation of the PCIe bus 4 lane Gen 1 control of digital front and rear I O and QDRII read write interface logic SFP module interface for 1 Gig Ethernet with DDR3 Memory PCle Interface Features PCIe Bus...

Page 10: ...SW API WIN64 consists of low level drivers and Dynamic Link Libraries DLLs that are compatible with a number of programming environments The DLL functions provide a high level interface to boards elim...

Page 11: ...to applying power Card Cage Considerations Refer to the specifications section for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements...

Page 12: ...The tables included in the P16 Input Data Register and P16 Output Data Register sections can be used to map the LVCMOS signal to the signal names given in this table The 2 5 volt IOStandards availabl...

Page 13: ...table below The rear I O can alternatively be defined for LVDS_25 Low Voltage Differential Signaling in the user constraints file The 2 5 volt IOStandards available are listed in the Virtex 6 User Gu...

Page 14: ...are powered by 2 5 volts and thus will support the 2 5 volt IOStandards The IOSTANDARD attribute can be set in the user constraints file UCF The example design defines the Front I O to LVCMOS25 low v...

Page 15: ...9 SFP1_RX_P A31 SFP1_RX_N A32 SFP2_TX_P A34 SFP2_TX_N A35 SFP2_RX_P A37 SFP2_RX_N A38 3 3V B10 B13 B16 B53 2 5V B1 B2 B3 12V A2 GND A5 A8 A11A14 A17 A20 A23 A26 A17 GND A20 A23 A26 A27 A30 A33 A36 A39...

Page 16: ...to reconfigure the flash memory until after you have tested and become familiar with the XMC 6VLX as provided in the example design 2 After you are familiar with the XMC 6VLX and have tested it using...

Page 17: ...nfiguration of the Xilinx FPGA 1 Set DIP switch 5 to the OFF position This will enable selection of the Platform flash device and disable selection of the BPI flash device Set DIP switch 2 and 3 to th...

Page 18: ...ses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address Since this boa...

Page 19: ...Flash memory 4M Space BAR0 5 64 bit Memory Base Address for Memory Accesses to QDRII memory 16M Space BAR2 6 10 Not Used 11 Subsystem ID 0x6301 XMC 6VLX240F 0x6302 XMC 6VLX365F 0x6303 XMC 6VLX240 0x6...

Page 20: ...gisters Table 3 2 BAR0 Registers Note that any registers bits not mentioned will remain at the default value logic low BAR0 Base Address Size Description 0x00000000 0x0000FFFF 64K Reserved 0x00010000...

Page 21: ...ister 0x00100018 31 0 Interrupt Vector Register 0x0010001C 31 0 Master Enable Register Interrupt Status Register Read Write BAR0 0x00100000 This Interrupt Status register ISR at BAR0 base address offs...

Page 22: ...this interrupt 0 Disabled 1 Enabled 1 This bit when set indicates an AXI CDMA interrupt See the CDMA section for source of this interrupt 0 Disabled 1 Enabled 31 2 Reserved 0 NA 1 NA Interrupt Enable...

Page 23: ...g interrupt input An interrupt input that is active and masked by writing a 0 to the corresponding bit in the Interrupt Enable register will remain active until cleared by acknowledging it Unmasking a...

Page 24: ...the correct Interrupt Vector Address Master Enable Register Read Write BAR0 0x0010001C This is a 2 bit read write register The two bits are mapped to the two least significant bits of the location Th...

Page 25: ...ach descriptor has an address pointer to the next sequential descriptor to be processed The last descriptor in the chain generally points back to the first descriptor in the chain but it is not requir...

Page 26: ...Progress 1 Reset in Progress 3 This bit controls the transfer mode of the CDMA Setting this bit to a 1 causes the AXI CDMA to operate in a Scatter Gather mode Note This bit must only be changed when t...

Page 27: ...Scatter Gather disabled Simple Mode Only the default value of the port is zeros 31 24 Interrupt Delay Time Out This value is used for setting the interrupt delay time out value The interrupt time out...

Page 28: ...ion software drivers to determine if Scatter Gather Mode can be utilized 0 Scatter Gather not included 1 Scatter Gather is included 4 DMA Internal Error This bit indicates that an internal error has b...

Page 29: ...e error condition 0 No Scatter Gather Internal Errors 1 Scatter Gather Internal Error CDMA Engine halts 9 Scatter Gather Slave Error This bit indicates that an AXI slave error response has been receiv...

Page 30: ...rupt event has been generated on a delay timer time out If the Interrupt on Delay Timer bit 13 of the CDMA Control register 1 an interrupt is generated from the AXI CDMA A CPU write of 1 clears this b...

Page 31: ...tware application in Scatter Gather Mode to set the starting address of the first transfer descriptor to execute for a Scatter Gather operation The address written corresponds to a 32 bit system addre...

Page 32: ...matches the tail descriptor pointer When the AXI CDMA is in Scatter Gather Mode a write by the software application to this register causes the AXI CDMA Scatter Gather Engine to start fetching descri...

Page 33: ...data transfers The address value written can be at any byte offset Note The software application should only write to this register when the AXI CDMA is Idle CDMA Destination Address Register Read Wri...

Page 34: ...he desired state for interrupt generation on transfer completion 3 Write the desired transfer source address to the Source Address register at 0xA0018 The transfer data at the source address must be v...

Page 35: ...erved Table 3 16 AXI BAR0 Aperture Base Address 0x01000000 0x01FFFFFF 16M Window into PCIe Interface AXI BAR0 Aperture Base Address The following is an example of how the AXI BAR0 aperture base addres...

Page 36: ...tus 0x000F0148 0x000F0204 31 0 See Xilinx DS820 Memory Map 0x000F0208 31 0 Address Translation Register Upper AXIBAR2PCIEBAR_0U 0x000F020C 31 0 Address Translation Register Lower AXIBAR2PCIEBAR_0L 0x0...

Page 37: ...e address in system memory to which the DMA transfer is to read or write An example of the c code used to set this register with the physical address is shown below AXI Base Address Translation Config...

Page 38: ...te that any registers bits not mentioned will remain at the default value logic low BAR0 Base Addr Bit s Description 0x300000 31 0 Interrupt Status Clear 0x300004 31 0 Reserved 0x300008 31 0 DDR Memor...

Page 39: ...8 0x3011FF 31 0 Reserved 0x301200 31 0 P16 Input Data Register 0x301204 31 0 P16 Output Data Register 0x301208 0x30FFFF 31 0 Reserved Front I O Interrupt Status Clear Register Read Write BAR0 0x300000...

Page 40: ...form Flash Configuration is selected 16M byte 1 BPI Flash Configuration is selected 32M byte 1 Platform Flash Address Flow Through 0 Write logic low has no effect 1 Write logic high to select address...

Page 41: ...own 1 Link is up 24 31 Reserved 0 Write logic low has no effect 1 Write logic high has no effect Flash Introduction The BPI flash memory has 32M bytes of program code or data storage available The Pla...

Page 42: ...16 are used to select one of 256 flash 64 Kword blocks as shown in this figure A15 to A14 are used to select one of the four 16 Kword top blocks Figure 3 24 Platform Flash Memory Map The most signific...

Page 43: ...Register Description 0 Buffered Enhanced Factory Programming BEFP x BEFP is not available x BEFP is not available 1 Block Lock Status 0 Block not locked 1 Block locked 2 Program Suspend Status 0 Progr...

Page 44: ...by writing logic 1 to bit 2 of this register at base address plus 0x300204 Bit 3 of this register is used to set Platform Flash Asynchronous Mode Write to Flash Control register at 0x300204 with bit...

Page 45: ...is used to erase the contents of the addressed flash block A flash bit cannot be programmed from logic 0 to logic 1 Only an erase block operation can convert logic 0 back to logic 1 Prior to reprogra...

Page 46: ...ead address 0x300208 flash data at address 0x0 is 0x3A3A Simple Platform Flash Programming Example 1 Write 0x2 to address 0x300100 Platform flash address flow though is selected 2 Write 0x8000 to addr...

Page 47: ...ut from the ADC can be converted to temperature by using the following equation 15 273 1024 975 503 ADCcode C e Temperatur The 10 bits digitized and output from the ADC can be converted to voltage by...

Page 48: ...ll channels of this register are fixed as input channels Table 3 28 BAR0 Front Input Data Register Note that any registers bits not mentioned will remain at the default value logic low Register Bit Ch...

Page 49: ...h 3 interrupts via data bits 0 to 3 Bits 4 to 31 are not used and will always read as 0 All channel interrupts are disabled set to 0 following a power on or software reset Reading or writing to this r...

Page 50: ...w i e a 0 in the output channel data register A 1 bit means that an interrupt will occur when the output channel is high i e a 1 in the output channel data register Note that no interrupts will occur...

Page 51: ...nnel read operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as input channels Table 3 30 BAR0 Rear Input Data Register Note that any registers bits not menti...

Page 52: ...transfers All channels of this register are fixed as output channels Table 3 31 BAR0 Rear Output Data Register Note that any registers bits not mentioned will remain at the default value logic low Reg...

Page 53: ...ad only register Channel read operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as input channels Table 3 32 BAR0 P16 Input Data Register Note that any regis...

Page 54: ...Channel write operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as output channels Table 3 33 BAR0 P16 Output Data Register Note that any registers bits not...

Page 55: ...o maximize data throughput between the Field I O s and the controlling processor There is automatic DMA initiator available that will trigger upon a user set condition See AXI CDMA Registers for more...

Page 56: ...8 U11 DDR3 SDRAM 128M x 16 2Gb x4 8Gb or 1GB U2 Virtex 6 FPGA XC6VLX240 or XC7VLX365 16 x 4 x1 x1 U12 U13 QDRII SRAM 2M x 36 72Mb x2 144Mb or 18MB U14 IPMI Serial EEPROM 512 x 8 4Kb or 512B 36 x 2 U27...

Page 57: ...U9 U10 and U11 are 128 Meg x 16 bit 2Gb in size All four device add to 8Gb or 1GByte total memory The DDR3 interface is implemented in FPGA banks 15 16 26 and 36 DCI VRP N resistor connections are im...

Page 58: ...ansceivers GTX MGTs The XMC 6VLX provides access to 18 MGTs Eight 8 of the MGTs are wired to the PCIe x8 Endpoint P15 XMC connector Eight 8 of the MGTs are wired to the P16 XMC connector Two 2 MGTs ar...

Page 59: ...28X FTG64C Platform Flash device is used with an onboard 48 MHz oscillator to configure the Virtex 6 FPGA in less than 100ms from power valid This is required by the PCI Express Card Electromechanical...

Page 60: ...quiescent low power state Otherwise the Platform Flash can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption To drive the FPGA BPI_Flash pin...

Page 61: ...and 2 respectively Figure 4 2 Multi Purpose Select DIP Switch Table 4 1 Configuration Details In JTAG mode switch5 On selects FPGA access to BPI Flash Alternatively set switch5 Off for FPGA access to...

Page 62: ...re 4 3 Power Distribution Table 4 2 Power System Devices Device Reference Designator Description Power Rail Name Power Rail Current LTM4602 U18 FPGA VCCINT 1 0V 6 0 A LTM4602 U19 VCCO DDR3 QDRII 1 5V...

Page 63: ...e temperature and power supply conditions via JTAG and the PCIe bus interface The system monitor is located in the center of the Virtex 6 die The System Monitor function is built around a 10 bit 200 k...

Page 64: ...ect by copying the Acromag example project deleting any unnecessary peripherals and then adding the user defined functionality The XMC V6 block diagram shows the structure of the example system with p...

Page 65: ...t may be desirable to use Scatter Gather mode in which case a descriptor list can be set up in QDR memory to move data to or from host memory In order for the AXI CDMA core to move data from the QDR m...

Page 66: ...mbedded system consists of the following IP blocks Microblaze processor DDR3 SDRAM two Ethernet SFP ports with supporting DMA controllers UART interrupt controller timer and the common peripherals ove...

Page 67: ...t and axi_dma in Xilinx Platform Studio Knowing how the hardware is configured will allow you to focus on the particular sections of the Xilinx documentation that are pertinent Host Peripherals The ho...

Page 68: ...attached to srec_bootloader srec_bootloader This program is embedded in the example FPGA configuration bitstream It is loaded into block RAM memory at configuration time and begins executing when rese...

Page 69: ...Gbs This configuration is compatible with both the 1000Base X and the 1000Base T SFP modules available from Acromag util_bufr_core Core A pcore was created to instantiate a regional clock buffer in X...

Page 70: ...core Acromag modified library files Acromag has modified two of the Xilinx supplied source files used to build a board support package that includes the Lightweight Internet Protocol LWIP library The...

Page 71: ...section describes the steps required to create an S record file that can be loaded into FLASH memory and executed upon initial application of power From within SDK open the project properties to disp...

Page 72: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 70 http www acromag com 70 www acromag com...

Page 73: ...next power cycle the boot loader will copy the program from FLASH to DDR3 memory and execute the program from DDR3 memory Please note a modified version of the Xilinx bootloader code is embedded into...

Page 74: ...l description of the Error Reference source not found project the network adaptor ettings on the host PC s need to be modified The hardware will support both SFP modules on XMC 6VLX240 365F to work at...

Page 75: ...side the FPGA Ping requests can be made by typing ping 192 168 1 XXX into a Window CMD terminal This will send out ICMP Internet Control Message Protocol packets and the Ethernet core inside the Xilin...

Page 76: ...oduct XMC 6VLX240F This directory is the parent for design files that are specific to the particular variant of XMC V6 Subdirectories further organize the design files into Xilinx tool specific folder...

Page 77: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 75 http www acromag com 75 www acromag com...

Page 78: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 76 http www acromag com 76 www acromag com Click on the address tab to display the address map...

Page 79: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 77 http www acromag com 77 www acromag com The DDR3 SDRAM is currently located at address 0x40000000...

Page 80: ...acromag com 78 www acromag com We will move the base address of the DDR3 SDRAM to address 0x80000000 Click in the Base Address column of the DDR3_SDRAM row and change the 4 to 8 and then click somewhe...

Page 81: ...10 79 http www acromag com 79 www acromag com The cacheable range address parameter of the microblaze configuration must also be updated Select the Bus Interfaces tab and then right click on microblaz...

Page 82: ...romag Inc Tel 248 295 0310 80 http www acromag com 80 www acromag com Click Next 4 times to arrive at the Caches page Update the instruction and data cache base and high addresses to align with the ne...

Page 83: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 81 http www acromag com 81 www acromag com The cacheable address range is currently set to 0x40000000 to 0x4FFFFFFF...

Page 84: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 82 http www acromag com 82 www acromag com Set the instruction and data cache base addresses and high addresses to 0x80000000 to 0x8FFFFFFF...

Page 85: ...0310 83 http www acromag com 83 www acromag com Click OK to accept the changes Next exit XPS and return to ISE to compile the updated system Right click on system_top in the Heirarchy pane and then se...

Page 86: ...ww acromag com After the place and route process is completed the hardware definition files used by SDK will need to be updated Click on system_i in the Heirarchy pane and notice the processes availab...

Page 87: ...ANUAL Acromag Inc Tel 248 295 0310 85 http www acromag com 85 www acromag com ISE will ask for confirmation of the SDK workspace path Confirm that the path is C XMC V6 XMC 6VLX240F SDK Click on OK SDK...

Page 88: ...RAM address is not reflected in all of the places it needs to be The memory_config_g_c c file used by the srec_bootloader program must be updated with the DDR3 SDRAM address In the Project Explorer pa...

Page 89: ...elf program is included in the FPGA bitstream that is loaded into the FPGA on power up A new bitstream must be generated that includes the updates to the FPGA firmware as well as the updated software...

Page 90: ...nerate Programming File process has completed launch iMPACT to covert the bit file to a mcs file If iMPACT doesn t automatically open the project file XMC 6VLX640F ipf then click on FILE Open and navi...

Page 91: ...C 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 89 http www acromag com 89 www acromag com Double click on Generate File in the iMPACT Processes pane This process will create the file XMC 6VLX240F m...

Page 92: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 90 http www acromag com 90 www acromag com Click on the Boundary Scan tab...

Page 93: ...stream will be written to the platform FLASH on the XMC V6 A Platform USB II cable or equivalent must be connected to the JTAG port Right Click on the FLASH device attached to the FPGA in the diagram...

Page 94: ...ot_loader program copies the lwip_echo_server_dual program from FLASH memory to DDR3 SDRAM and then executes the lwip_echo_server_dual program in DDR3 SDRAM The linker script for the program lwip_echo...

Page 95: ...MANUAL Acromag Inc Tel 248 295 0310 93 http www acromag com 93 www acromag com The base address of the DDR3 SDRAM has been updated automatically but the code data and heap sections are currently locat...

Page 96: ...g com Select DDR3_SDRAM_S_AXI_BASEADDR from the drop down list for each of code section data section and heap and stack Enter 1048576 for the heap size and the stack size 1 MB will be displayed in the...

Page 97: ...UAL Acromag Inc Tel 248 295 0310 95 http www acromag com 95 www acromag com The project will automatically re build and create a new lwip_echo_server_dual srec file This is the file that will be writt...

Page 98: ...Acromag Inc Tel 248 295 0310 96 http www acromag com 96 www acromag com Run the Acromag PCIe6VLX demo program Enter 2 to Locate Choose board Enter the appropriate number to select the XMC V6 variant t...

Page 99: ...MC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 97 http www acromag com 97 www acromag com Enter Y to indicate the FPGA is configured with the Acromag example design Select function 4 Flash command...

Page 100: ...com If BPI is not the currently selected FLASH then select function 1 Toggle selected flash device Select 8 Write code file to flash Select 2 Other and enter the path to the lwip_echo_server_dual sre...

Page 101: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 99 http www acromag com 99 www acromag com After the programming operation is complete enter 99 twice and answer Y to exit the program...

Page 102: ...s by writing messages to the serial port To view the progress messages displayed on power up a separate PC must be running a terminal emulator program such as hyper terminal connected to COMM3 The ser...

Page 103: ...ration for Use section have been followed Also refer to the documentation of your board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a...

Page 104: ...0 mA Max 100 mA 12 5 VDC as 12V 5 Typical 1 8A Max 2 0A 12 VDC 5 0mA On Board 1 0V Power to Virtex 6 FPGA Current Rating Maximum available for the user programmable FPGA 1 0V 5 6A Maximum Operating Te...

Page 105: ...C6VLX240T 1FF1156 241 152 Logic Cells 3 650 Kbit Distributed RAM 416 36 Kbit Block RAMs 768 DSP48E1 Slices 12 Mixed Mode Clock Managers 2 Interface Blocks for PCI Express 4 Ethernet MACs XC6VLX365T 1F...

Page 106: ...7 1 or equivalent This connector provides 64 rear I O connections The rear I O P4 PMC connector connects directly to banks 25 and 35 of the FPGA Bank 25 and 35 Vcco pins are powered by 2 5 volts and t...

Page 107: ...r devices together DDR3 memory devices are wired to FPGA banks 15 16 26 and 36 DCI VRP N resistor connections are implemented on banks 15 and 36 DCI functionality in bank 15 is achieved in the UCF by...

Page 108: ...n parallel with the XCF128 Platform Flash XL There are a total 256 addressable blocks each 64 Kwords PCIe Bus Interface XMC Compatibility Conforms to PCI Express Base Specification v2 0 and XMC Specif...

Page 109: ...XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 107 http www acromag com 107 www acromag com...

Page 110: ...4Mb or 18MB U14 IPMI Serial EEPROM 512 x 8 4Kb or 512B 36 x 2 U27 USB to UART Bridge 16 x 1 P16 VITA 42 XMC Connector P15 VITA 42 XMC Connector J4 64 pin Rear I O Connector U4 BPI Flash Memory Bite wi...

Page 111: ...ss to Sanitize Power Down Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No Type EEPROM Flash etc Flash Size 16Mby...

Page 112: ...tial Acromag release 17 DEC 12 B LMP LMP Removed reference to extended temperature grade products Added power supply requirements 14 AUG 13 C LMP LMP Additional text added to pages 64 65 describing Et...

Page 113: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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