1. Introduction
8
LAN Interface (DP83905)
The National Semiconductor DP83905 AT/LANTIC provides the interface between the
STD bus and the on-board Local Area Network (LAN) bus The DP83905 also provides
the network interface portion of the LAN bus.
The LAN Bus
The LAN bus consists of the packet RAM and Network Interface. LAN Interface
configuration values are programmed into an external EEPROM when the device is set
up. These values are automatically loaded into on-board registers when the board is
powered up.
Depending on the configuration, the DP83905, with some external help, decodes both
memory and I/O addresses when accessing the on-board PROM socket, RAM, or
Network Interface.
The Network Interface
The Network Interface provided by the DP83905 implements all Media Access Control
(MAC) layer functions for transmission and reception of Ethernet packets, in accordance
with both the IEEE 802.3 standard and pre-IEEE 802.3 standards.
It also contains an internal First In First Out (FIFO) buffer and arbitration logic to control
access to the packet RAM. The DP83905 includes:
•
Support for physical, multicast, and broadcast address filtering
•
Provision for three levels of loopback
•
Implementation of buffer management
The DP83905 provides complete IEEE 802.3 protocol and electronics with the only
exception being the packet RAM.
Serial Interface (DP83905)
The National Semiconductor DP83905 also provides Manchester encoding, decoding,
and collision detection for the Serial Interface. The 83905 includes the following:
•
10 Mbps encoding and decoding
•
Loopback capability for diagnostics
•
Isolation from Ethernet cable
The DP83905 interfaces the ZT 8995 to the Ethernet cable via an external Attachment
Unit Interface (AUI) drop cable, the on-board Transceiver Interface (8392), or twisted-
pair cabling.
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