2. Getting Started
23
PHYS1..0
BPWR
D7
D6
D5
D4
D3
D2
D1
D0
Register: Configuration Register B
Address: Base + 0Eh
Physical Layer Interface
Access: Read and Write
IO16
EELOAD
00 10BaseT
Link Test Pulse Gen./Integrity Check
0 = Enabled
1 = Disabled
0 = Address Decode
1 = Slave R/W Strobe
IO16CON
01 10Base2
10 AUI (10Base5)
11 Reduced Squelch Twisted Pair
GDLNK
CHRDY
Drive /IOCHRDY
0 = After Slave Strobe is Asserted
1 = After BALE is Asserted
BE
Bus Error
Boot ROM Write Cycle Protect
0 = Disabled
1 = Enabled
EEPROM LOAD
0 = Disabled
1 = Enabled
PHYS1..0 (D1..0) - The Physical Layer Interface bits select the type of physical layer
being used on the board. This could be 10BaseT, 10Base2, AUI (10Base5) or Reduced
Squelch Twisted Pair. The ZT 8995 comes configured to use 10BaseT. [PHYS1,0 =
0,0].
GDLNK (D2) - This bit enables link test pulse generation and integrity checking when
using twisted pair. It can also be read to indicate status. Link pulse generation and
checking is disabled by writing a 1 to this bit. The ZT 8995 is shipped with link testing
enabled.
IO16CON (D3) - One of two methods of generating /IO16 is chosen using this bit. In
normal operation, /IO16 is driven off of the address decode. /IO16 can be configured to
be driven from the slave read or write strobe by this bit. The ZT 8995, as shipped, will
generate /IO16 from address decode. [IO16CON = 0].
CHRDY (D4) - The way the AT/LANTIC drives /IOCHRDY can be selected by
programming this bit. When low, the AT/LANTIC will drive /IOCHRDY after a slave
strobe is asserted. When high, the AT/LANTIC will drive /IOCHRDY on BALE being
asserted; this may be required when being used with some chipsets that sample
/IOCHRDY early. The ZT 8995, as shipped, will drive /IOCHRDY after slave strobe is
asserted.
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