SARA-N2 / N3 series - System integration manual
UBX-17005143 - R13
Design-in
Page 76 of 95
C1-Public
Figure 50
shows an example of a schematic diagram where a SARA-N3
“0
0
” product version is
integrated into an application board using most of the available interfaces and functions.
3V6
GND
100uF
10nF
SARA-N3 series
52
VCC
53
VCC
51
VCC
68pF
18
RESET_N
Application
processor
Open
drain
output
TP
12
TXD
13
RXD
10
RTS
11
CTS
TP
TP
TXD
RXD
CTS
1.8V DTE
0R
0R
62
ANT_DET
10k
27pF
ESD
68nH
56
Connector
External
antenna
33pF
ANT
39nH
15pF
15pF
100nF
VCC
1V8
GND
15
PWR_ON
Open
drain
output
TP
RTS
7
RI
RI
SDA
SCL
26
27
33pF
SIM card holder
CCVCC (C1)
CCVPP (C6)
CCIO (C7)
CCCLK (C3)
CCRST (C2)
GND (C5)
33pF 33pF
100nF
41
VSIM
39
SIM_IO
38
SIM_CLK
40
SIM_RST
33pF
ESD ESD ESD ESD
Test-Point
28
29
RXD_FT
TXD_FT
Test-Point
Test-Point
42
GPIO5
ESD
470k
SW1
SW2
4
V_INT
1k
RSVD
GND
GND
Network
indicator
3V6
16
GPIO1
VSEL
21
17
TXD_AUX
19
RXD_AUX
25
GPIO4
24
GPIO3
23
GPIO2
59
ANT_BT
6
DSR
8
DCD
9
DTR
2
V_BCKP
ADC1
33
Figure 50: Sample schematic diagram to integrate a SARA-N3
“0
0
” product version using
most of the interfaces