Ublox SARA-N2 Series, Руководство по системной интеграции

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SARA-N2 / N3 series - System integration manual
UBX-17005143 - R13 Design-in Page 60 of 95
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2.6 Serial interfaces
2.6.1 Main primary UART interface
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The SARA-N2 modules do not support hardware flow control functionality over the CTS and RTS
pins. The SARA-N2 modules do not include the DTR , DSR , DCD and RI pins.
☞
The “00” product version of SARA -N3 modules do not support DTR , DSR and DCD functionality:
the lines can be left unconnected, and the DTR input line can also be connected to GND.
☞
If voltage translators are needed, it is recommended to use ones providing partial power-down
feature, so that the DTE supply can be also ramped up before V_INT supply.
2.6.1.1 Guidelines for main primary UART circuit design
Guidelines for SARA-N3 series modules ’ TXD, RXD, RTS, CTS and RI lines connection
If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim
MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chips
provide the translation from 1.8 V / 2.8 V to 3.3 V, while the Maxim chip provides the translation from
3.3 V to RS-232 compatible signal level.
If a 1.8 V application processor (DTE) is used, and the generic digital interfaces of the module (DCE)
are configured to operate at 1.8 V (
V_INT = 1.8 V, if the VSEL pin is connected to GND: see 1.5.3 ), the
circuit should be implemented as described in Figure 33 .
TxD
Application processor
(1.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
SARA-N3 series
(1.8V DCE)
15 TXD
12 DTR
16 RXD
13 RTS
14 CTS
9 DSR
10 RI
11 DCD
GND
0
Ω
0
Ω
TP
TP
21
VSEL
Figure 33: SARA- N3 series’ UART application circuit with TXD, RXD, RTS, CTS and RI lines connection (1.8 V DTE / 1.8 V DCE)
If a 2.8 V application processor (DTE) is used, and the generic digital interfaces of the module (DCE)
are configured to operate at 2.8 V (
V_INT = 2.8 V, if the VSEL pin is left unconnected: see 1.5.3 ), the
circuit should be implemented as described in Figure 34 .
TxD
Application processor
(2.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
SARA-N3 series
(2.8V DCE)
15
TXD
12 DTR
16
RXD
13 RTS
14 CTS
9
DSR
10
RI
11
DCD
GND
0
Ω
0
Ω
TP
TP
21 VSEL
Figure 34: SARA- N3 series’ UART application circuit with TXD, RXD, RTS, CTS and RI lines connection (2.8 V DTE / 2.8 V DCE)
If a 3.0 V application processor is used and the generic digital interfaces of the module are configure
to operate at 1.8 V (
V_INT = 1.8 V, if the VSEL pin is connected to GND: see 1.5.3 ), then the 1.8 V UART
of the module (DCE) can be connected to the 3.0 V UART of the application processor (DTE) by means
of an appropriate unidirectional voltage translators providing partial power down feature (thus the