SARA-N2 / N3 series - System integration manual
UBX-17005143 - R13
System description
Page 8 of 95
C1-Public
1.2
Architecture
summarize the architecture of SARA-N2 series and SARA-N3 series modules
respectively, describing the internal blocks of the modules, consisting of the RF, Baseband and Power
Management main sections, and the available interfaces.
Memory
V_INT
38.4 MHz
32.768 kHz
RF
transceiver
Power
management
Baseband
ANT
SAW
Filter
Switch
PA
VCC (supply)
DDC (I
2
C)
UART
SIM
Secondary UART
RESET_N
GPIO
Antenna detection
Figure 1: SARA-N2 series modules block diagram
☞
The “02" product version of
SARA-N2 series modules do not support the following interfaces,
which should not be driven by external devices:
o
Antenna detection
o
DDC (I2C) interface
26 MHz
32.768 kHz
RF
transceiver
Baseband
ANT
Switch
PA
V_BCKP (RTC)
V_INT (I/O)
Power
management
VCC (supply)
Memory
Reset
Power-on
SIM
SIM card detection
UART (Primary main)
UART (Secondary auxiliary)
DDC (I2C)
ADC
GPIOs
Antenna detection
VSEL (I/O voltage selection)
UART (Flashing & tracing)
BT
ANT_BT
Figure 2: SARA-N3 series block diagram
☞
The “00" product version
of SARA-N3 series modules do not support the following interfaces,
which should not be driven by external devices:
o
Bluetooth interface (ANT_BT)
o
Secondary auxiliary UART interface (UART AUX)
o
DDC (I2C) interface