SARA-N2 / N3 series - System integration manual
UBX-17005143 - R13
Design-in
Page 64 of 95
C1-Public
If the application board requires a RING indication to get notifications when an URC or when new data
is available, the
CTS
line of SARA-N2 modules can be used for such a functionality. In this case the
circuit should be implemented as shown in
•
Connect DTE TxD output line with the TXD input pin of SARA-N2 modules
•
Connect DTE RxD input line with the RXD output pin of SARA-N2 modules
•
Connect DTE RI input line with the CTS output pin of SARA-N2 modules
•
Leave RTS line of the module unconnected and floating.
•
Use the same external supply rail (for example, at 3.3 V or 3.6 V) for both the SARA-N2 module and
the Application Processor (DTE), so that the interface of both devices operates at the same level,
considering that the UART interface of SARA-N2 modules operates at the VCC voltage level
TxD
Application processor
(3.3V DTE)
RxD
RI
GND
SARA-N2
(DCE)
12
TXD
13
RXD
10
RTS
11
CTS
GND
0
Ω
TP
0
Ω
TP
52
VCC
3V3
3V3
VCC
51
VCC
53
VCC
Figure 41: SARA-
N2 series’ UART interface application circuit with TXD, RXD and RING lines con
nection to 3.3 V DTE
Additional considerations
If a 1.8 V Application Processor (DTE) is used, the voltage scaling from any UART output of the module
(DCE), working at
VCC
voltage level (3.6 V nominal), to the apposite 1.8 V input of the DTE can be
implemented, as an alternative low-cost solution, by means of an appropriate voltage divider.
Consider the value of the pull-up integrated at the input of the Application Processor (DTE), if any, for
the correct selection of the voltage divider resistance values.
Mind that any DTE signal connected to the UART interface of the module has to be tri-stated or set
low before the turn-on of the supply
rail of the modules’ UART interfac
e (
VCC
for SARA-N2 modules,
V_INT
for SARA-N3 series modules), to avoid latch-up of circuits and allow a proper boot of the
module.
☞
There is
no
internal pull-up / pull-down inside the
TXD
input line of the SARA-N2 module, which is
assumed to be controlled by the external host once UART is initialized: to avoid an increase in
current consumption, consider to add an external pull-up resistor of about 47 k
to 100 k
, biased
by
VCC
module supply rail, if the
TXD
input is left floating by the external host in some scenario.
☞
An internal pull-up is integrated inside the
TXD
input line of the SARA-N3 series modules: an
external pull-up resistor is not required.
☞
ESD sensitivity rating of UART pins is 1 kV (HBM according to JESD22-A114). Higher protection
level could be required if the lines are externally accessible on the application board. Higher
protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG
varistor) close to accessible points.
2.6.1.2
Guidelines for main primary UART layout design
The UART serial interface requires the same consideration regarding electro-magnetic interference
as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog
inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.
