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2.12.5.2 Basic Operation of 1588V2
Software time-stamp vs. Hardware time-stamp
There are two techniques to time-stamp packets:
1. Software time-stamp occurs when the messages are handled by the software. Usually occurring in the message’s receive/
transmit interrupt service routine (ISR), the time-stamp is the current value of the system time.
2. Hardware time-stamp occurs when the messages physically arrive at or leave the device. The time-stamp operation is
executed by hardware, which maintains its own continuous time information.
Either time-stamp method is acceptable in IEEE 1588, but a hardware time-stamp can provide significantly better precision.
The OLT equipment provides HW time stamp.
Delay from Master-Clock Device to Slave-Clock Device, (Figure 2-)
At time Tm1, the master-clock device software reads the current local system time (Tm1, the software timestamp), inserts
it into a Sync message, and sends the message out. The message leaves the master-clock device at a later time, Tm1’, which
is the hardware time-stamp. It arrives at slave-clock hardware at Ts1’ (slave-clock device local time), and is received by the
slave-clock device software at a later time, Ts1. The software will read the hardware time-stamp to get Ts1’. If there is no
communication delay, Ts1’ should be equal to (Tm1’ + Tms), where Tms is the time difference between master clock and slave
clock. The protocol’s ultimate goal is to compensate for this difference.
After the Sync message has been sent, the master-clock device software reads the Sync message’s departure time, Tm1’,
through the time-stamping unit, inserts it into a Follow-up message, and sends that message out at Tm2. This message is
received by slave clock device software at Ts2. At this point, the slave-clock device software has the two times, Ts1’ (Sync arrival
time) and Tm1‘ (Sync departure time). The master-to-slave path delay, Tmsd, is determined by Equation Tmsd=(Ts1´+Tms)-Tm1´
Figure 2-17: Delay from Master-Clock Device to Slave-Clock Device
Delay from Slave-Clock Device to Master-Clock Device (Figure 2-)
The DelayReq message is sent by the slave-clock devices, and the DelayResp message is sent by the master-clock device
in response. With these messages, the slave-clock devices can calculate the communication path delay from the slave-clock
device to the master-clock device.
At time Ts3 (Figure 3), the slave-clock device software reads the current local system time (Ts3), inserts it into a DelayReq
message, and sends the message out. After the message is sent, the slave-clock device software reads the time-stamp to get
the departure time of the message, Ts3’, and waits for the response from the master-clock device.
The DelayReq message arrives at the master-clock device at a later time, Tm3’, and is processed by the master software at
Tm3. The software then reads the time-stamp to get the arrival time, Tm3’, puts it into the DelayResp message, and sends to
a slave-clock device at Tm4. When the slave-clock device software receives the DelayResp message at Ts4, it can extract the
time, Tm3’, and calculate the slave-to-master delay, Tsmd, by Equation Tsmd=Tm3´-(Ts3´+Tms).