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Operating Basics
GTS1063 and GTS1250 GBIC Test Systems Instruction Manual
17
This is an input through which you can supply a 1.25 GHz (GTS1250) or
1.0625 GHz (GTS1063) clock to externally clock the transmit patterns. To
enable the input, pull the remote interface EXT_CLK_ENA pin low.
The quality of the clock determines the amount of jitter; the outgoing data will
have the same timing jitter content as the EXT CLK IN signal.
The Remote Interface is implemented with a 25-pin, male D connector on the
rear panel. This interface serves five separate interface requirements:
H
TTL input 3-bit remote control of Tx Pattern selection (when in REM
mode).
H
TTL output flags, for GBIC Tx Fault and Rx LOS, and TTL GBIC laser
disable control (TX DISABLE).
H
Serial Clock and bidirectional Data (similar to I2C) for GBIC serial-ID
communication (also known as the GBIC MOD_DEF pins).
H
GBIC VDD +5 V supply current or voltage overload flags, overload RESET,
GBIC +5 V VDD current and voltage monitor signals, GBIC +5 V VDD
supply offset, and GBIC power enable.
H
Miscellaneous control inputs: front-panel lockout and external-clock enable.
GND
Serial ID
Communication
Lines to GBIC
MOD_DEF(2)
MOD_DEF(1)
MOD_DEF(0)
TX pattern BIT1
TX pattern BIT0
TX pattern BIT2
TX DISABLE
1
REM Flag
GND
GND
RESERVED
GBICPWR_ENA
RX_LOS
TX_FAULT
V OFFSET
I Overload
V Overload
Overload RESET
1
I monitor
V monitor
TTL Remote
Selection of Tx
Patterns
RESERVED
EXT_CLK_ENA
1
FRNT_PNL_LOCK
1
GND
GBIc Flags
and Monitor
Remote TX Control and
GBIC Mod_Def
1
14
1
Active low control input
Figure 7: Rear Remote Interface connector pinout
External Clock Input
Remote Interface
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