Tektronix 2445, Инструкция по эксплуатации

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Theory o f Operation—2445 Service
A t 1.4 jus after STARTDOT goes HI, U2995 pin 13
(QH) goes HI to produce the REST signal, indicating that
the current dot cycle is complete and the Dot Cycle Gener­
ator is at REST. If the readout ACTIVE/ADDRESSABLE
mode bit at U2970C pin 10 is still HI, the REST signal
going HI produces a HI DOTOK signal (next dot is allowed)
at pin 8. This HI applied to pin 10 of U2890C, along w ith
any of the possible dot requests from the Dot Start
Governor, w ill initiate another STARTDOT cycle fo r the
next dot of the display. As long as the Display Sequencer
holds the readout active line (ROA) LO, U2885B, U2890D,
and U2890B o f the Dot Start Governor w ill automatically
initiate dot cycles as soon as the previous one ends (REST
goes HI), until the Refresh Prioritizer is decremented to
zero.
When the last dot of the character is called from the
Character ROM, the EOCH b it (DD7) applied to latch
U2905 at pin 8 (in the Mode Select Logic circuitry) is LO.
A t the end o f that dot display cycle, the GETDOT signal
clocks the LO EOCH b it into latch U2905. The latched b it
becomes the EOCH1 signal (end of character, delayed one
dot request) and is applied to U2855B, along w ith the
already LO EOCH bit, to reset Dot Counters U2870A and
B. The least-significant bits to the Character ROM address
pins (AO through A4) are then zeros, and the firs t dot of
the next character is addressed. The Horizontal and Vertical
DACs don't write this first dot position data into their
registers until t he end of the next GETDOT signal. That
same GETDOT signal also clocks EOCH1 into U2905 which
becomes EOCH2 at pin 6 (end of character, delayed by two
dot requests). EOCH2 is applied to AND-gate U2970A and
disables the gate prior to the time the Dot Cycle Generator
attempts to unblank the crt fo r the first dot display; thus
the first dot of a character is never displayed.
Disabling the unblanking path fo r the first dot of each
character in the manner just described allows the more
radical voltage changes between characters to settle before
the actual display of the next character begins. When the
dot data for one of these undisplayed dots also has the
EOCH b it set LO, it is a space character, and the display is
advanced to the next character.
Dot Timer
The Dot Timer, composed of U2890A and U2830A and
B, generates three, time-related signals used to synchronize
the display and maintain the proper sequencing of the
individual character dots.
The two least-significant bits of the Dot Timer, from
U2830B pins 11 and 10, are reset at the beginning of a
dot cycle by a LO STARTDOT signal applied to the reset
input of the counter via U2890A. As the dot-display cycle
begins, the STARTDOT signal returns HI and the Dot
Timer begins counting in a binary fashion. The 10-MHz
clock applied to pin 13 is divided by two to produce the
5-MHz clocking signal at output pin 11. The 5-MHz clock
sequences the Dot Cycle Generator through the various
phases of the dot-display cycle. The REFRESH output
signal from U2830A pin 4 updates the Refresh Prioritizer
as each subframe is displayed.
A third clock, from U2830A pin 6, occurs at approx­
imately 8-jus intervals and allows any pending d ot requests
to generate a ROR signal to the Display Sequencer via
flip-flop U2950B. (Readout request generation is described
in the Dot Start Governor discussion.)
HIGH VOLTAGE POWER
SUPPLY AND CRT
The High Voltage Power Supply and CRT circuit
(diagram 8) provides the voltage levels and control circuitry
fo r operation o f the cathode-ray tube (crt). The circuitry
consists o f the High Voltage Oscillator, the High Voltage
Regulator, the Cathode Supply, the Anode M ultiplier, the
DC Restorer, Focus Amplifiers, the CRT, and the various
CRT Control circuits.
High Voltage Oscillator
The High Voltage Oscillator transforms power obtained
from the —15 V unregulated supply into the various ac
levels necessary fo r the operation of the c rt circuitry. The
circuit consists prim arily of transformer T1970 and
switching transistor Q1981 connected in a power oscillator
configuration. The low-voltage oscillations set up in the
primary winding of T1970 are raised by transformer action
to high-voltage levels in the secondary windings. These ac
secondary voltages are applied to the DC Restorer, the
Cathode Supply, and the Anode M ultiplier circuits that
provide the necessary crt operating potentials.
Oscillation occurs due to the positive feedback from the
primary winding (pin 4 to pin 5) to the smaller base-drive
winding (pin 3 to pin 6) that provides base drive to
switching transistor Q1981. The frequency of oscillation is
approximately 50 kHz and is determined prim arily by the
resonant frequency of the transformer.
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