Tektronix 2445, Инструкция по эксплуатации

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Maintenance— 2445 Service
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rupt cycles are checked to ensure that succeeding interrupts
occur not more than 4.5 ms apart (5600 “E” cycles).
Test checks: Interrupt Timer circuitry.
SWITCH STUCK (Test 02). The front-panel, momentary-
contact switches are scanned, checking for a closed switch.
At power up, the test runs immediately.
By holding one of the momentary switches in a closed
position when power is first applied, this test will fail, and
the Diagnostic Monitor will be entered. When the test is
started from the Diagnostic Monitor, a one-half second de­
lay is incorporated to allow the COUPLING (test start)
switch to return to its normal (open) position. Table 6-4 de­
fines the error codes that may be encountered when a
switch is detected as closed.
N OTE
When the user presses the COUPLING switch to stop
this test, an error code may be generated. This is nor­
mal and does not indicate an actual failure.
Test checks:
Momentary switches, row scanning circuit­
ry, and column scanning circuitry.
READOUT BOARD (Test 03).
This two-part test checks
the interface to the Readout Board from the Microprocessor
and the character RAM circuits.
Processor Interface Test —The Microprocessor loads
the three, eight-bit shift registers with an alternating bit pat­
tern that is then shifted back to the processor for
comparison.
Test checks: Data Registers, data strobes (clocks), and
the data input and output lines.
RAM Test
—A “1” is rotated through each byte of the
Readout RAM, one bit at a time. Each time an additional bit
is rotated into the byte, the byte is loaded into the processor
interface and clocked back to the processor for comparison.
The byte is then restored to its original content, and each
successive byte is tested in the same manner.
Test checks: Readout RAM addressing, Readout RAM
data lines, and RAM read/write capability.
EAROM (Test 04). Three checks are performed on the
EAROM to verify its contents and the interface circuitry.
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read, modified, and then reread to verify functioning of the
device interface.
Test checks: EAROM input and output lines, EAROM
mode control, EAROM reading and writing, and the EAROM
clock.
Checksum Test
—The contents of locations containing
calibration constants are checksummed using a sprial-add
technique. The result is compared to the contents of loca­
tion 0 (the checksum generated at the time of calibration).
Test checks:
EAROM addressing and EAROM
contents.
Parity Test
— As each of the calibration constants is read
for the Checksum test above, the parity of each 14-bit word
is checked.
Test checks: EAROM data retention and EAROM
reading.
MAIN BOARD (Test 05).
The AUTO LVL triggering fea­
ture (a routine stored in firmware) is operated to detect the
peaks of a Line Trigger signal. Detected peaks are com­
pared to expected values to verify operation (and calibra­
tion) of interrelated signal processing circuits.
Test checks:
Line Trigger source, the A Trigger genera­
tion circuitry, and Control DAC U2234 (located on the Con­
trol board).
Exerciser Routines
The Exerciser routines allow the operator to set and ex­
amine various bytes of control data used in determining in­
strument function.
POTS AND SWITCHES (Exerciser 01). This routine dis­
plays the values that the Microprocessor detects as the var­
ious digitized pots and switches are activated. The top line
of the ert display has the following format:
AA BB CC DEEE FF GG HI JJ KL
The format is defined as follows:
“AA” is the code of the most-recently-activated potenti­
ometer (see Table 6-8 for definition of pot codes).
“BB” is the current value (in hexadecimal) of pot AA.
“ CC” is the previous value (in hexadecimal) of pot AA.
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