Tektronix 2445, Инструкция по эксплуатации, Страница: 51 / 351

Theory o f Operation—2445 Service
data from the Microprocessor is applied asynchronously
to the buffered Data Bus. A t the end of the write cycle, the
R/W signal goes HI, and the reset to U2468B is removed.
The E signal also goes through a negative transition, and
data on the Microprocessor data bus lines is latched into
U2294. The next positive transition o f the 1.25-MHz E
signal (1/2 E cycle after the R/W signal goes HI) clocks the
HI level at U2468B pin 12 (the D input) to the Q output,
and the Q output (pin 8) goes LO. The 1/2 E cycle delay
between the time R/W goes HI and the time that the Q
output o f U2468B goes HI keeps Latch U2294 outputs
on long enough to meet the data hold time fo r the RAM.
A t the end o f that delay time, pin 1 o f U2294 goes HI,
and the Latch outputs are switched to the high-impedance
state to isolate it from the buffered Data Bus.
A write-enable signal to the RAM is generated by the
circuit composed of U2656C and U2556F. The processor
R/W signal is inverted by U2556F and NANDed w ith the
enable signal (E) by U2656C. The write enable to the RAM
at U2656C pin 9 is produced after the address data has
settled. This action prevents w riting to improper RAM
address locations.
READOUT FRAMING AND INTERRUPT TIMING.
Binary Counter U2668 is used to generate a readout­
framing clock to the Readout circuitry and a real-time
interrupt request to the Microprocessor via inverter
U2556E. The readout-framing clock is a regular square-
wave signal obtained from U2668 pin 14 by dividing the
1.25-MHz E signal from U2556C pin 6 by 1024 (210). This
clock tells the readout circuitry to load the next block
(subframe) o f readout information to be displayed. (See
“ Readout" description fo r further information concerning
the alphanumeric display.) The real-time interrupt request,
which occurs every 3.3 ms, is obtained from pin 2 by
dividing the E signal by 8192 (213).
When the real-time interrupt request occurs, IRQ (pin 4
o f U2092) goes LO, and the processor breaks from execu­
tion of its mainline program. The Microprocessor first
resets Binary Counter U2668 by setting pin 19 of U2043
(diagram 2) HI (to generate the reset), then it resets pin 19
LO to allow the counter to start again. A t this time, the
Microprocessor sets analog control voltages and reads
trigger status from the Display Sequencer (diagram 11).
When this is completed, it reverts back to the mainline
program.
In addition to the analog control and trigger status
update that occurs w ith each interrupt, on every fifth
interrupt cycle the Microprocessor also scans the front-
panel potentiometers. Every tenth interrupt cycle, scanning
the front-panel switches and checking the 50-12 DC inputs
fo r overloads is added to the previously mentioned tasks.
If all the tasks are not completed at the end o f one inter­
rupt cycle, the real-time interrupt request restarts the
analog updates, but as soon as those are accomplished,
the Microprocessor w ill pick up w ith its additional tasks
where it was before the interrupt occurred. This continues
until all tasks are completed. If any pot or switch changes
are detected, the Miroprocessor updates the analog control
voltages and the control register data to reflect those
changes prior to reverting back to the mainline program
instructions.
ANALOG CONTROL
The Analog Control circuitry (diagram 2), under Micro­
processor control, reads the front-panel controls and sets
various analog control voltages to reflect these front-panel
settings. The calibration constants determined during
instrument calibration and the last “ stable" front-panel
setup conditions (unchanged fo r approximately seven
seconds) are stored in EAROM (elecrically-alterable read­
only memory). A t power-on the stored front-panel infor­
mation is used to return the instrument to its previous
operating state.
Status Buffer
Data transfer from the Analog Control circuitry to
the Microprocessor is via Status Buffer U2108. Data bits
applied to the input pins are buffered onto the Data Bus
when enabled by the Address Decode circuitry. Via the
Status Buffer, the processor is able to (1) determine the
settings of front-panel pot and switches, (2) read the
EAROM data, (3) find out if the readout display should
be switched on or o ff, (4) determine if a triggered sweep is
in progress, and (5) read the contents o f the Readout RAM.
When disabled, the buffer outputs are switched to high
impedance states to isolate them from the buffered Data
Bus.
Front Panel Switch Scanning
The Front Panel Switches are arranged in a matrix o f ten
rows and five columns. Most of the row-column inter­
sections contain a switch. When a switch is closed, one of
the row lines is connected to one of the column lines
through a diode. Reading o f the switches is accomplished
by setting a single row line LO and then checking each of
the five column iines sequentially to determine if a LO is
present (signifying that a switch is closed). A fter each of
the five columns has been checked, the current row line
is reset HI and the next row line is set LO fo r the next
column scan cycle. A complete Front Panel Switch scan
consists of setting aii ten row iines LO in sequence and
performing a five-column scan fo r each o f the rows.
Row lines are set LO when the Microprocessor writes
a LO to one of the flip-flops in octal registers U2034 and
3-9