Tektronix 2445, Инструкция по эксплуатации

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Theory of Operation—2445 Service
selected ROM is enabled, and data from the selected
address location is read out of the ROM.
Of the bottom 32k-bytes of addresses, only the lowest
8k-bytes are further decoded. When addresses in this
8k-byte range are decoded, the YO output of U2480
enables decoder U2770. Thisthree-line-to-eight-line decoder
separates the lowest 8k-byte address block into 2k-byte
blocks. Any address falling into the lowest 2k-byte block
of addresses w ill cause U2770 to generate an enable to the
RAM (random-access memory) U2496. Addresses in the
next highest 2k-byte block of addresses w ill enable U2580
to do the next stage o f address decoding. The remaining
2k-byte blocks decoded by U2770 are not used.
The level o f decoding performed by U2580 uses address
bits A6, A7, and A8 to separate the addresses w ithin the
2k-byte block of addresses 0800 to OFFF into 32 groups
of 64 addresses each. Address bits A9 and A10 are not used
in the decoding scheme, so each o f these 32 blocks is not
uniquely identified. This results in four duplicate sections
w ithin the address block, each consisting o f eight groups
of 64 addresses. The upper three sections in the address
space are never used; therefore, decoding by U2580 may be
more simply thought of as eight groups o f 64 address
locations. Addresses w ithin these eight groups generate
control signals to other portions of the instrument.
The final level of address decoding is done by four-line-
to-sixteen-line decoder U2596. When enabled by the Y7
output of U2580, this decoder separates the highest 64-
address group decoded by U2580 into 16 individual control
signals. In this level of decoding, address bits A4 and A5 are
not decoded, so that the 64 possible addresses consist of
four overlayed blocks of 16 addresses each.
Each of the control signals generated by the Address
Decode circuitry are present only as long as the specific
address defining that signal is present on the Address Bus.
However, four of the addressable control signals decoded
by U2596 are used to either set or reset flip-flops U2656B
and U2656D. The control signals are, in effect, latched and
remain present to enable multiplexers U2335 (diagram 2)
and U170 (diagram 4). When enabled, these multiplexers
route analog control signals from DAC (digital-to-analog
converter) U2235 (diagram 2) to the various analog control
circuits.
Read-only Memory (ROM)
The Read-only Memory consists o f four, 8k-byte ROMs
that contain the operating instructions (firmware) used to
control processor (and thus oscilloscope) operation.
Addresses from the Microprocessor that fall w ithin the top
32k-bytes of addressable space cause one of the four
read-only memory integrated circuits to be enabled. (See
Address Decode description.) Instructions are read out of
the enabled ROM (or PROM) 1C from the address location
present on its 13 address input pins (AO through A12).
The eight-bit data byte from the addressed location is
placed onto the buffered Data Bus (BDO through BD7) to
be read by the Microprocessor.
Random-Access Memory (RAM)
The RAM consists of integrated circuit U2496 and
provides the Microprocessor w ith Ik-byte of temporary
storage space for data that is developed during the execu­
tion of a routine. The RAM is enabled whenever an address
in the lowest 2k-byte o f addresses is placed on the Address
Bus. When w riting into the RAM, the write-enable signal
(WE) on pin 21 of U2496 is set LO along w ith the chip
enable (CE) signal on pin 18. A t the same time, the output-
enable signal (OE) on pin 20 is HI to disable the RAM out­
put drivers. Data is then w ritten to the location addressed
by the Microprocessor. If data is to be read from the RAM,
the WE signal is set HI to place the RAM in the read mode,
and the OE signal is set LO to enable the output drivers.
This places the data from the addressed location on the
buffered Data Bus where it can be read by the Micro­
processor.
Timing Logic
The Timing Logic circuit composed o f U2468B, U2556F,
U2556C, and U2656C generates time- and mode-dependent
signals from control signals output from the Microprocessor.
The enable (E) signal output from the Microprocessor is
a 1.25-MHz square wave used to synchronize oscilloscope
functions to processor timing.
Data applied to the Address Bus, Data Bus, and various
control signals are allowed to settle (become valid) before
any of the addressed devices are enabled. This is accom­
plished by switching the E signal HI a short time after each
processor cycle begins. The delayed enable signal is inverted
by U2556C to provide the active LO signal (E) that enables
the Address Decode circuit after the Address Bus has
settled.
Read-Write Latch U2468B is used to delay the read/
write signal (R/W) from the Microprocessor to meet hold­
time requirements o f the RAM. A t the same time, it gen­
erates delayed read and write enabling signals o f both
polarities to meet the requirements of Buffer U2194 and
Latch U2294 (in the Microprocessor Data Bus) and various
other devices in the Readout circuitry (diagram 7).
When R/W goes LO fo r a write cycle, Read-Write Latch
U2468B is reset, and the Q output (pin 9) is held LO.
Latch U2294 is in its transparent state at this time, and
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