A-40
Sun Netra X4450 Server Service Manual • August 2008
2E
Initializes all the output devices.
31
Allocates memory for ADM module and decompress it. Gives control to ADM module for
initialization. Initializes language and font modules for ADM. Activate ADM module.
33
Initializes the silent boot module. Set the window for displaying text information.
37
Displaying sign-on message, CPU information, setup key message, and any OEM specific
information.
38
Initializes different devices through DIM.
39
Initializes DMAC-1 and DMAC-2.
3A
Initializes RTC date and time.
3B
Tests for total memory installed in the system. Also, Check for DEL or ESC keys to limit
memory test. Displays total memory in the system.
3C
By this point, RAM read-write test is completed, program memory holes or handle any
adjustments needed in RAM size with respect to NB. Tests if HT module found an error in
boot block and CPU compatibility for MP environment.
40
Detects different devices (Parallel ports, serial ports, and coprocessor in CPU, etc.)
successfully installed in the system and update the BDA, EBDA, etc.
50
Programming the memory hole or any kind of implementation that needs an adjustment
in system RAM size if needed.
52
Updates CMOS memory size from memory found in memory test. Allocates memory for
Extended BIOS Data Area from base memory.
60
Initializes NUM-LOCK status and programs the KBD typematic rate.
75
Initializes Int-13 and prepares for IPL detection.
78
Initializes IPL devices controlled by BIOS and option ROMs.
7A
Initializes remaining option ROMs.
7C
Generates and writes contents of ESCD in NVRAM.
84
Logs errors encountered during POST.
85
Displays errors to the user and gets the user response for error.
87
Executes BIOS setup if needed or requested.
8C
After all device initialization is done, programmed any user selectable parameters relating
to NB/SB, such as timing parameters, noncacheable regions, and the shadow RAM
cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during
Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on
setup questions. Get the DRAM scrub limits from each node. Workaround for erratum No.
101 applied here.
8D
Builds ACPI tables (if ACPI is supported).
TABLE A-4
POST Code Checkpoints
(Continued)
Post Code
Description
