Appendix A
Configuring BIOS and POST
A-39
06
Does read-write test to CH-2 count reg. Initialize CH-0 as system timer. Install the
POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch
vector to POSTINT1ChHandlerBlock.
C0
Early CPU Init Start-Disable Cache-Init Local APIC.
C1
Sets up boot strap processor information.
C2
Sets up boot strap processor for POST. This action includes frequency calculation, loading
BSP microcode, and applying user requested value for GART Error Reporting setup
question.
C3
Errata workarounds applied to the BSP (No. 78 & No. 110).
C5
Enumerates and sets up application processors. This action includes microcode loading,
and workarounds for errata (No. 78, No. 110, No. 106, No. 107, No. 69, No. 63).
C6
Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata No.
106, No. 107, No. 69, and No. 63 if appropriate. In case of mixed CPU steppings, errors are
sought and logged, and an appropriate frequency for all CPUs is found and applied. Note:
APs are left in the CLI HLT state.
C7
The HT sets link frequencies and widths to their final values. This routine gets called after
CPU frequency has been calculated to prevent bad programming.
0A
Initializes the 8042 compatible keyboard controller.
0B
Detects the presence of PS/2 mouse.
0C
Detects the presence of keyboard in KBC port.
0E
Testing and initialization of different input Devices. Also, update the kernel variables.
Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
Decompress all available language, BIOS logo, and silent logo modules.
13
Initializes PM regs and PM PCI regs at Early-POST. Initialize multihost bridge, if system
supports it. Set up ECC options before memory clearing. REDIRECTION causes corrected
data to written to RAM immediately. CHIPKILL provides 4 bit error
det/corr
of x4 type
memory. Enable PCI-X clock lines in the 8131.
20
Relocates all the CPUs to a unique SMBASE address. The BSP will be set to have its entry
point at A000:0. If fewer than 5 CPU sockets are present on a board, subsequent CPUs
entry points will be separated by 8000h bytes. If more than 4 CPU sockets are present,
entry points are separated by 200h bytes. CPU module will be responsible for the
relocation of the CPU to correct address. Note: APs are left in the INIT state.
24
Decompresses and initializes any platform specific BIOS modules.
30
Initializes System Management Interrupt.
2A
Initializes different devices through DIM.
2C
Initializes different devices. Detects and initializes the video adapter installed in the
system that have optional ROMs.
TABLE A-4
POST Code Checkpoints
(Continued)
Post Code
Description
