Appendix A
Configuring BIOS and POST
A-37
00d3
Memory detections and sizing in boot block, cache disabled, I/O APIC enabled.
01d4
Testing base 512KB memory. Adjusting policies and cache first 8MB.
01d5
Boot block code is copied from ROM to lower RAM. BIOS is now executing out of RAM.
01d6
Key sequence and OEM specific method is checked to determine if BIOS recovery is
forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.
01d7
Restoring CPUID: Moving boot block-runtime interface module to RAM: determining
whether to execute serial flash.
01d8
Decompressing runtime module into RAM. Storing CPUID information in memory.
01d9
Copying main BIOS into memory.
01da
Giving control to BIOS POST.
0004
Checking CMOS diagnostic byte to determine if battery power is OK and CMOS
checksum is OK. If the CMOS checksum is bad, update CMOS with power-on default
values.
00c2
Setting up boot strap processor for POST. This action includes frequency calculation,
loading BSP microcode, and applying user requested value for GART Error Reporting
setup question.
00c3
Errata workarounds applied to the BSP (No. 78 and No. 110).
00c6
Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata No.
106, No. 107, No. 69, and No. 63 if appropriate.
00c7
HT sets link frequencies and widths to their final values.
000a
Initializing the 8042 compatible keyboard controller.
000c
Detecting the presence of keyboard in KBC port.
000e
Testing and initialization of different input devices. Traps the INT09h vector, so that the
POST INT09h handler gets control for IRQ1.
8600
Preparing CPU for booting to OS by copying all of the context of the BSP to all application
processors present. Note: APs are left in the CLI HLT state.
de00
Preparing CPU for booting to OS by copying all of the context of the BSP to all application
processors present. Note: APs are left in the CLI HLT state.
8613
Initializing PM regs and PM PCI regs at early-POST. Initialize multihost bridge, if system
supports it. Setup ECC options before memory clearing. Enable PCI-X clock lines in the
8131.
0024
Decompressing and initializing any platform specific BIOS modules.
862a
BBS ROM initialization.
002a
Generic Device Initialization Manager (DIM) - Disable all devices.
042a
ISA PnP devices - Disable all devices.
TABLE A-3
POST Codes
(Continued)
Post Code
Description
