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SDS5000XSeries Digital Oscilloscope Service Manual
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using the method below.
Figure 32
Test points for clock
Table 18
Clock parameters of the Acquisition System
Test Point Clock Domain
Level
Description
TP44
PLL Reference Clock
LVCMOS33 Typical 10 MHz
TP43
Reference Clock
Locked
LVCMOS33
High level indicates PLL locked
Low level means PLL lock failed
8.6
To Check the Processor Board
The processer board is mounted on the acquisition board as a daughter
card.
8.6.1
Check the processor power supplies
Check the power rails. Find and measure those test points using a
multi-meter.