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Date Code 20020129
Differential, Restricted Earth Fault,
3-39
Overcurrent, Voltage, and Frequency Elements
SEL-387E Instruction Manual
51Qn Negative-Sequence Inverse-Time Element
The 51Qn element logic compares the magnitude of the calculated negative-sequence current,
3I2Wn, to the pickup setting, 51QnP. If the calculated negative-sequence current exceeds the
pickup level, a logical 1 asserts at one input to the AND gate at the center. The torque-control
SEL
OGIC
control equation, 51QnTC, determines the other AND input. If 51QnTC is true, Relay
Word bit 51Pn asserts and the inverse curve begins timing.
As with phase inverse-time element logic, four settings define the curve. In this case 51QnP is
the pickup, 51QnC defines the curve equation, 51QnTD defines the time dial, and 51QnRS
determines how the curve resets.
Curve time-out causes Relay Word bit 51QnT to assert. When the current drops below pickup,
51Qn deasserts and the element resets according to the setting for 51QnRS. At the completion of
the reset, Relay Word bit 51QnR asserts. This bit normally is at logic state 1, when the element is
at rest during normal system operation. You can use the
TAR
command to verify the state of the
bit. You can use the Level 2 serial port command
RES
or the front-panel RESET51 function
under the OTHER button to force the bit to a logical 1 during element testing. This saves time if
you have chosen electromechanical reset.
51Nn Residual Inverse-Time Element
The 51Nn element compares the magnitude of the calculated residual current, IRWn, to the
pickup setting, 51NnP. If calculated residual current exceeds the pickup level, a logical 1 asserts
at one input to the AND gate at the center. The torque-control SEL
OGIC
control equation,
51NnTC, determines the other AND input. If 51NnTC is true, Relay Word bit 51Nn asserts and
the inverse curve begins timing.
The settings defining the curve in this case are 51NnP for the pickup setting, 51NnC for the
particular curve equation, 51NnTD for the time dial, and 51NnRS for the curve reset.
Curve time-out causes Relay Word bit 51NnT to assert. When the current drops below pickup,
51Nn deasserts and the element resets according to the setting for 51NnRS. At the completion of
the reset, Relay Word bit 51NnR asserts. This bit normally is at logic state 1, when the element is
at rest during normal system operation. You can use the
TAR
command to verify the state of the
bit. You can use the Level 2 serial port command
RES
or the front-panel RESET51 function
under the OTHER button to force the bit to a logical 1 during element testing.
51PC1 and 51NC1 Combined Overcurrent Elements
The combined overcurrent elements operate on summed input currents to two windings.
Elements 51PC1 and 51NC1 use phase and residual current from Windings 1 and 2. See Figure
3.22.
Содержание SEL-387E
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