Samsung S3C2416, Руководство пользователя

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REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR
13-8
1.5 INDIVIDUAL REGISTER DESCRIPTIONS
1.5.1 REAL TIME CLOCK CONTROL (RTCCON) REGISTER
The RTCCON register consists of 9 bits. It controls the read/write enable of the CLKSEL, CNTSEL and CLKRST
for testing.
RTCEN bit can control all interfaces between the CPU and the RTC, Therefore it must be set to 1 in an RTC
control routine to enable data read/write after a system reset. Before power off, the RTCEN bit is cleared to 0 to
prevent inadvertent writing into BCD counter register.
CLKRST is counter reset for 2
15
Clock divider.(reference to Figure 15-1)
Before RTC clock setting, 2
15
Clock divider must be reset for exact RTC operation.
Register Address R/W Description Reset Value
RTCCON 0x57000040 R/W RTC control register 0x00
RTCCON Bit Description Initial State
TICsel2 [8:5] Tick Time clock select2.
0 = clock period of 1/16384 second select
1 = clock period of 1/8192 second select
2 = clock period of 1/4096 second select
3 = clock period of 1/2048 second select
4 = clock period of 1/128 second select
5 = clock period of 1 second select
6 = clock period of 1/1024 second select
7 = clock period of 1/512 second select
8 = clock period of 1/256 second select
9 = clock period of 1/64 second select
10 = clock period of 1/32 second select
11 = clock period of 1/16 second select
12 = clock period of 1/8 second select
13 = clock period of 1/4 second select
14 = clock period of 1/2 second select
0x0
TICsel [4] Tick Time clock select1.
0 = Clock period select at TICsel2
1 = Clock period of 1/32768 second
0
CLKRST [3] RTC clock count reset.
0 = No reset
1 = Reset
0
CNTSEL [2] BCD count select.
0 = Merge BCD counters
1 = Reserved (Separate BCD counters)
0
CLKSEL [1] BCD clock select.
0 = XTAL 1/215 divided clock
1 = Reserved (XTAL clock only for test)
0
RTCEN [0] RTC control enable.
0 = Disable 1 = Enable
Note:
Only BCD time count and read operation can be performed.
0